STLVD2101BF Ver la hoja de datos (PDF) - STMicroelectronics
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STLVD2101BF Datasheet PDF : 9 Pages
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STLVD210
LVDS TIMING CHARACTERISTICS (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise noted. Typical
values are at TA = 25°C) (Note 1)
Symbol
Parameter
Test Conditions
Value
Unit
Min. Typ. Max.
tTLH Transition Time Low to High
tTHL Transition Time High to Low
tPHL, tPLH Propagation Delay to Output
fMAX Maximum Input Frequency
tSKEW Bank Skew
Part-to-Part Skew
Pulse Skew
RL = 100 Ω, CL = 5 pF
220 300
ps
220 300
ps
2
2.5
ns
700 900
MHz
50
ps
100
60
NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground
unless otherwise specified.
SPECIFICATION OF CONTROL REGISTER
The STLVD210 is provided with a 11 bit shift register with a Serial In and a Control Register. The purpose
is to enable or power of each output clock channel. The STLVD210 provides two working modality:
PROGRAMMED MODE (EN=1)
The shift register have a serial input to load the working configuration. Once the configuration is loaded
with 11-clock pulse, another clock pulse loads the configuration into the control register. The first bit on
the serial input line enables the outputs Qb4 and Qb4, the second bit enables the outputs Qb3 and Qb3
and so on. The last bit is the fewer significations. To restart the configuration of the shift register a reset
of the state machine must be done with a clock pulse on CK and the EN set to Low. The control register
can be configured on time after each reset.
STANDARD MODE (EN=0)
In Standard Mode the STLVD210 isn’t programmable, all the clock outputs are enabled.
TRUTH TABLE OF STATE MACHINE INPUTS
EN
SI
CK
OUTPUT
L
X
X
All Outputs Enable
H
L
First stage stores "L", other stages store the data of previous stage
H
H
First stage stores "H", other stages store the data of previous stage
L
X
Reset of the state machine, Shift register and Control Register
SERIAL INPUT SEQUENCE
BIT#10
N.A.
BIT#9
Qa0
BIT#8
Qa1
BIT#7
Qa2
BIT#6
Qa3
BIT#5
Qa4
BIT#4
Qb0
BIT#3
Qb1
BIT#2
Qb2
BIT#1
Qb3
BIT#0
Qb4
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