28F016XS Ver la hoja de datos (PDF) - Intel
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28F016XS Datasheet PDF : 54 Pages
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28F016XS FLASH MEMORY
E
Number
-001
-002
-003
REVISION HISTORY
Description
Original Version
Removed support of the following features:
• All page buffer operations (read, write, programming, Upload Device Information)
• Command queuing
• Software Sleep and Abort
• Erase all Unlocked Blocks and Two-Byte Write
• RY/BY# Configuration as part of the Device Configuration command
Changed definition of “NC.” Removed “No internal connection to die” from description.
Added “xx” to Upper Byte of Command (Data) Definition in Sections 4.3 and 4.4.
Modified parameters “V” and “I” of Section 5.1 to apply to “NC” pins.
Increased IPPR (VPP Read Current) for VPP > VCC to 200 µA at VCC = 3.3V/5.0V.
Changed VCC = 5.0V DC Characteristics (Section 5.5) marked with Note 1 to indicate
that these currents are specified for a CMOS rise/fall time (10% to 90%) of <5 ns
and a TTL rise/fall time of <10 ns.
Corrected tPHCH (RP# High to CLK) to be a “Min” specification at VCC = 3.3V/5.0V.
Corrected the graphical representation of tWHCH and tEHCH in Figures 15 and 16.
Increased Typical “Byte/Word Program Times” (tWHRH1A/tWHRH1B) for VPP = 5.0V (Sec.
5.13): tWHRH1A from 16.5 µs to 29.0 µs and tWHRH1B from 24.0 µs to 35.0 µs at VCC =
3.3V
tWHRH1A from 11.0 µs to 20.0 µs and tWHRH1B from 16.0 µs to 25.0 µs at VCC = 5.0V.
Increased Typical “Block Program Times” (tWHRH2/ tWHRH3) for VPP = 5.0V (Section 5.13):
tWHRH2 from 2.2 sec to 3.8 sec and tWHRH3 from 1.6 sec to 2.4 sec at VCC = 3.3V
tWHRH2 from 1.6 sec to 2.8 sec and tWHRH3 from 1.2 sec to 1.7 sec at VCC = 5.0V.
Changed “Time from Erase Suspend Command to WSM Ready” spec name to “Erase
Suspend Latency Time to Read;” Modified typical values and Added Min/Max values
at VCC =3.3/5.0V and VPP =5.0/12.0V (Section 5.13).
Minor cosmetic changes throughout document.
Added 3/5# pin to Pinout Configuration (Figure 2), Product Overview (Section 1.1) and
Lead Descriptions (Section 2.1)
Modified Block Diagram (Figure 1): Removed Address Counter; Added 3/5# pin
Added 3/5# pin to Test Conditions of ICCS Specifications
Added 3/5# pin (Y) to Timing Nomenclature (Section 5.6)
Removed Note 7 of Section 5.7
Modified Device Configuration Code: Incorporated RY/BY# Configuration (Level Mode
support ONLY)
Modified Power-Up and Reset Timings (Section 5.10) to include 3/5# pin: Removed t5VPH
and t3VPH specifications; Added tPLYL, tPLYH, tYLPH, and tYHPH specifications
Added SSOP pinout (Figure 2) and Mechanical Specifications
Corrected TSOP Mechanical Specification A1 from 0.50 mm to 0.050 mm (Section 6.0)
Minor cosmetic changes throughout document.
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