28F016XS Ver la hoja de datos (PDF) - Intel

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Fabricante

28F016XS

16-MBIT (1 MBIT x 16, 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY

Intel 

E

28F016XS FLASH MEMORY

4.4 28F016XS—Enhanced Command Bus Definitions

Command

Read Extended Status Register

Notes

1

First Bus Cycle

Oper Addr Data(4)

Write

X

xx71H

Lock Block/Confirm

Upload Status Bits/Confirm

Device Configuration

Write

X

xx77H

2

Write

X

xx97H

3

Write

X

xx96H

Second Bus Cycle

Oper Addr Data(4)

Read RA GSRD

BSRD

Write

BA xxD0H

Write

X

xxD0H

Write

X

DCCD

ADDRESS

BA = Block Address

RA = Extended Register Address

PA = Program Address

X = Don’t Care

DATA

AD = Array Data

BSRD = BSR Data

GSRD = GSR Data

DCCD = Device Configuration Code Data

NOTES:

1. RA can be the GSR address or any BSR address. See Figures 5 and 6 for Extended Status Register memory maps.

2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the

actual lock-bit status.

3. This command sets the SFI Configuration allowing the device to be optimized for the specific sytem operating frequency.

4. The upper byte of the Data bus (D8–15) during command writes is a “Don’t Care” in x16 operation of the device.

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