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ST20-GP1

GPS PROCESSOR

STMicroelectronics 

ST20-GP1

3 Digital signal processing module

The ST20-GP1 chip includes 12 channel GPS correlation DSP hardware. It is designed to handle

twelve satellites, two of which can be initialized to support the RTCA-SC159 specification.

The digital signal processing (DSP) module extracts GPS data from the incoming IF (Intermediate

Frequency) data. There are a number of stages of processing involved; these are summarized

below and in Figure 3.1. After the 12 pairs of hardware correlators, the data for all channels are

time division multiplexed onto the appropriate internal buses (i.e. values for each channel are

passed in sequence, for example: I1, Q1, I2, Q2 ... I12, Q12, I1, Q1).

4 MHz IF

input

frequency

converter A

data

sampler

I correlator

(x 12)

Q correlator

(x 12)

frequency

converter B

DMA

interface

accumulator

Pseudo random

noise sequence

generator

(x 12)

Numerically

controlled

oscillator

ST20 CPU accessible

registers

Figure 3.1 DSP module block diagram

The main stages of processing are as follows:

Data sampling

This stage removes any meta-stability caused by the asynchronous input data coming from an

analogue source (the radio receiver). The data at this point consists of a carrier of nominally

4.092 MHz with a bandwidth of approximately ±1 MHz.

This stage is common to all 12 channels.

Frequency conversion (A)

The first frequency converter mixes the sampled IF data with the (nominal) 4.092 MHz signal. This

is done twice with a quarter cycle offset to produce I and Q (In-phase and Quadrature) versions of

the data at nominal zero centre frequency (this can actually be up to ±132 KHz due to errors such

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