ADG406 Ver la hoja de datos (PDF) - Analog Devices
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ADG406 Datasheet PDF : 20 Pages
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ADG406/ADG407/ADG426
VDD 1
NC 2
RS 3
S16 4
S15 5
S14 6
S13 7
S12 8
S11 9
S10 10
S9 11
GND 12
WR 13
A3 14
ADG426
TOP VIEW
(Not to Scale)
28 D
27 VSS
26 S8
25 S7
24 S6
23 S5
22 S4
21 S3
20 S2
19 S1
18 EN
17 A0
16 A1
15 A2
NC = NO CONNECT
Figure 10. 28-Lead PDIP/SSOP
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD
Most Positive Power Supply Potential.
2
NC
No Connect.
3
RS
Active Low Logic Input. When this pin is low, all switches are open, and address and enable latches registers are
cleared to 0.
4 to 11 S16 to S9 Source Terminal 16 to Source Terminal 9. These pins can be inputs or outputs.
12
GND
Ground (0 V) Reference.
13
WR
The rising edge of the WR signal latches the state of the address control lines and the enable line.
14 to 17 A3 to A0 Logic Control Input.
18
EN
Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin
is high, the Ax logic inputs determine which switch is turned on.
19 to 26 S1 to S8 Source Terminal 1 to Source Terminal 8. These pins can be inputs or outputs.
27
VSS
28
D
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground.
Drain Terminal. This pin can be an input or an output.
Table 9. Truth Table (ADG426)
A3
A2
A1
A0
EN
WR
RS
On switch
X
X
X
X
X
1
Retains previous switch condition
X
X
X
X
X
X
0
None (address and enable latches cleared)
X
X
X
X
0
0
1
None
0
0
0
0
1
0
1
1
0
0
0
1
1
0
1
2
0
0
1
0
1
0
1
3
0
0
1
1
1
0
1
4
0
1
0
0
1
0
1
5
0
1
0
1
1
0
1
6
0
1
1
0
1
0
1
7
0
1
1
1
1
0
1
8
1
0
0
0
1
0
1
9
1
0
0
1
1
0
1
10
1
0
1
0
1
0
1
11
1
0
1
1
1
0
1
12
1
1
0
0
1
0
1
13
1
1
0
1
1
0
1
14
1
1
1
0
1
0
1
15
1
1
1
1
1
0
1
16
Rev. B | Page 11 of 20
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