SPT8100SIT Ver la hoja de datos (PDF) - Signal Processing Technologies

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Fabricante

SPT8100SIT

16-BIT, 5 MSPS CMOS A/D CONVERTER

Signal Processing Technologies 

Figure 2a – Typical Interface Circuit

1.0 +

Gain Control

Reset

Output

Enable Clock

(active Hi) Input

AIN

Transformer

1.43K

REXT

.01

BIASC

BIASR

VCM

RS GS2 GS1

GS0

OE CLK

RDY

VIN+

RT

(50)

VIN–

SPT8100

16

D0–15

Mini-Circuit 0.1

T1-6T

+ 4.7

+

VRT

OVR

10 0.1 1nF

VRB

AVDD

DVDD

AGND

DGND OGND

OVDD

Logic

Interfacing

Circuit

0.1

10

+

+A5V

0.1

10

+

FB1

+A3.3/5V

+D3.3/5V

Figure 2b – Typical Interface Circuit

1.0 +

Gain Control

Reset

Output

Enable Clock

(active Hi) Input

AIN

.01

Transformer

1.43K

BIASC RS GS2 GS1 GS0

REXT

BIASR

VCM

OE CLK

RDY

VIN+

RT

(50)

VIN–

SPT8100

16

D0–15

Mini-Circuit 0.1 + 4.7

T1-6T

+

VRT

OVR

10 0.1 1nF

VRB

AVDD

DVDD

AGND

DGND

OGND OVDD

ƒs (MSPS) REXT (kΩ)

≤5

1.43

≤2

2.00

≤5

1.24

≤2

1.00

800 Ω ≤ REXT ≤ 2.5 kΩ

ƒIN

<2 MHz

<2 MHz

≥2 MHz

≥2 MHz

0.1

0.1

10 +

FB2

10

+

FB1

FB3

+A5V

Logic

Interfacing

Circuit

+D3.3/5V

Notes:

1. To avoid device latch-up, closely follow either figure 2a or 2b, depending on what is available in the system. The difference between

figure 2a and 2b is in the grounding.

2. FB = ferrite bead. FB1 must be placed as close to the device as possible.

3. REXT = 1.43 kΩ, optimized for ƒs = 5 MSPS. Refer to the above table for recommended value of REXT with respect to ƒs and ƒIN.

4. RT is AIN source termination resistor.

5. Power supplies and references pins must have adequate decoupling. Surface-mount capacitors are highly recommended. The

smallest value of capacitors are to be placed as close to the pin as possible.

SPT

6

SPT8100

5/12/00

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