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SPT8100SIT

16-BIT, 5 MSPS CMOS A/D CONVERTER

Signal Processing Technologies 

DEVICE OVERVIEW

The SPT8100 combines a high-resolution 5 MSPS 16-bit

ADC, a built-in reference, and a programmable gain amp-

lifier (PGA) with resistive input impedance in a 44-pin

package.

The device includes a digitally calibrated pipeline ADC,

which is calibrated on assertion of a simple reset signal. The

combination of low noise, high linearity, a high-input imped-

ance buffer (with programmable gain), wideband S/H, on-

board voltage references, and simple digital interface

(16-bit parallel output word synchronous with the master

sampling clock) makes the SPT8100 extremely easy to use

in a wide variety of systems.

For optimum performance, the analog inputs should be

driven differentially, and may be AC-coupled or DC-coupled

to a source. Typical applications include high-performance

data acquisition systems, automatic test equipment, and

wideband digital communications receivers such as wire-

less basestations.

OPERATIONAL DESCRIPTION

The following sections describe in greater detail individual

blocks and functions of the SPT8100.

The incoming analog differential signal (maximum level 5 V

peak-to-peak differential) enters the device at the pins

VIN+/VIN–. The analog signal path is partitioned into a pro-

grammable gain amplifier (PGA) and an ADC. The PGA has

maximum gain of +20 dB; the gain is set by the digital con-

trol signals GS0 to GS2.

The output of the PGA is fed directly to the ADC, which

samples at a rate equal to the CLK frequency and outputs a

16-bit wide parallel word. The ADC uses a pipeline multi-

stage architecture. Latency is 6 clock cycles.

Figure 1 – Device Initialization Timing

PWR ON

AIN

ADC CLOCK

The chip requires a single low-jitter clock to be applied at the

CLK pin, with nominal 40–60% duty cycle. All clock genera-

tion is performed internally and all converter and S/H clocks

in the ADC path are directly derived from CLK.

If the sample rate is changed by more than a factor of 2, the

device must be recalibrated using the RS (reset) pin.

DEVICE STARTUP/INITIALIZATION SEQUENCE

Note: This initialization sequence is required. Without

it, the device will not work.

Allow sufficient time for the analog blocks on the SPT8100

to power on and come up to their quiescent DC states.

Allowance may also be needed for thermal time constants

associated with the package/board.

On powerup, the SPT8100’s RS (reset) should be held low

for at least three clock cycles. The power supply voltages

applied to the device must be stable during this time. The

clock signal (CLK) must be running for at least three clock

cycles prior to the rising edge of RS , and must continue

running.

When the RS signal goes from low to high, calibration is

initiated. RDY is driven low two clock cycles after the rising

edge of RS , and will stay low for 150 ms with a 5 MHz clock.

When the initialization is complete, RDY returns high and

the device is ready for normal operation. Note that the cali-

bration of the ADC can be interrupted (before completion)

by changing the RS signal from high to low, which will cause

another reset to occur. When RS goes from low back to

high, another calibration cycle will begin.

RDY cannot be tri-stated: it is always driven either high or

low. The CLK clock must be constantly running throughout

the initialization phase until RDY is deasserted. Note that

N+8

N+7

N+4

N+5 N+6

CLK

RS

RDY

3 clock cycles min

DOUT

Requires external reset on powerup

2 clock cycles

5 ns typ

Initialization period: 150 ms with 5 MHz clock

24 ns typ

INVALID DATA

N N+1 N+2

SPT

4

SPT8100

5/12/00

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