SPT8100SIT Ver la hoja de datos (PDF) - Signal Processing Technologies
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SPT8100SIT Datasheet PDF : 10 Pages
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ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
AVDD ........................................................................ +6 V
DVDD ........................................................................ +6 V
OVDD ........................................................................ +6 V
Input Voltages
Analog Input ................................... –0.5 V to VDD +0.5 V
CLK Input .................................................................. VDD
AVDD – DVDD ..................................................... ±100 mV
Delta between AGND, DGND, and OGND ....... ±100 mV
Output
Digital Outputs ...................................................... 10 mA
Temperature
Operating Temperature ............................. –40 to +85 °C
Junction Temperature ........................................ +175 °C
Lead Temperature (soldering 10 seconds) ........ +300 °C
Storage Temperature .............................. –65 to +150 °C
Note 1: Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions
in typical applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, AVDD=DVDD=+5.0 V, OVDD= 3.3 V, ƒS=5 MSPS, 2.5 VPP input span, REXT=1.43 kΩ, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
MIN
SPT8100
TYP
MAX UNITS
Resolution
16
Bits
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
Gain Error1
Offset Error2
V
V
VI
–7.5
V
–5
±1.25
±0.5
+7.5
+5
LSB
LSB
%FSR
%FSR
Analog Input (into PGA)
Differential Input Voltage Range
VIN+, VIN–
Input Capacitance
Input Resistance3
PGA Gain = 0 dB
Input Bandwidth4
Input Common Mode Voltage Range
V
IV
IV
V
V
1.1
5
5.5
11
2.35
VPP
15 pF
kΩ
MHz
3.6 V
Programmable Gain Amp
Composite Input-Referred
PGA Gain = 0 dB
V
Noise Floor
PGA Gain = 20 dB
V
PGA Range
ƒIN > 300 kHz
V
PGA Gain Steps3
VI
PGA Gain Accuracy
VI
45.0
8.0
20
3,6,12,15,18,20
±0.3
nV/√Hz
nV/√Hz
dB
dB
dB
Conversion Characteristics
Maximum Conversion Rate
Pipeline Delay (Latency)
Reset Pulse Time (RS)
Reset Calibration Time
FS = 5 MSPS
VI
5
IV
IV
3
V
150
MHz
6 Clock Cycles
Clock Cycles
ms
References and External Bias
VRT – VRB (Internal Ref)
Bias Resistor Range (External)
VCM Output Voltage
VCM Output Current
VRT
VRB
VI
2.375
IV
800
IV
2.23
IV
IV
3.45
IV
0.95
2.5
1430
2.35
3.65
1.15
2.625 V
2500 Ω
2.47 V
50 µA
3.85 V
1.35 V
1 Total gain error of PGA and ADC using internal references.
2 Total offset error of PGA and ADC relative to mid-scale.
3 See table I for input resistance as a function of PGA gain.
4 Input bandwidth is a frequency to which the fundamental energy drops by 3 dB
SPT
2
SPT8100
5/12/00
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