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Fabricante

SP9500

12–Bit, Voltage Output D/A Converter

Signal Processing Technologies 

0

DNLE, INLE Plots

CODE

USING THE SP9500

External Reference

The R-2R DAC input resistance is code depen-

dent and is minimum (11kΩ) at code 1365 and

2731. And, it is nearly infinite at code 0. Be-

cause of the code-dependent nature of the refer-

ence inputs, a high quality, low output imped-

ance amplifier should be used to drive the VREF

and AGND inputs.

Serial Clock and Update Rate

The SP9500 maximum serial clock rate (SCLK)

is given by 1/(t +t ) which is approximately

CH CL

12.5 MHz. The digital word update rate is lim-

ited by the chip select period, which is 12 X

+0.5 lsb

DNLE

-0.5 lsb

+0.5 lsb

INLE

-0.5 lsb

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SCLK periods plus the CS high pulse width tCSW.

This is equal to a 1 µs or 1 MHz update rate.

However, the DAC settling time to 12–Bits is 7.5

µs, which for full scale output transitions would

limit the update rate to 125 kHz.

Logic Interface

The SP9500 is designed to be compatible with

TTL and CMOS logic levels. However, driving

the digital inputs with TTL level signals will

increase the power consumption of the part by

300 µA. In order to achieve the lowest power

consumption use rail-to-rail CMOS levels to

drive the digital inputs.

DIN

1

SHIFT

REGISTER

DDAACC

RREEGGISTTEERR

12 LATCH

12

VREF

DAC

Figure 1. Detailed Block Diagram

AGND

+

–

VOUT

VREF

DIN

+

–

AGND

VDAC

Figure 2. Transfer Function

WHERE…

VOUT

VOUT = VDAC

( ) VDAC =

DIN

4096

x (VREF - AGND) + AGND

SP9500DS/04

SP9500 12-Bit, Voltage Output D/A Converter

5

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