MGA-86563-BLK Ver la hoja de datos (PDF) - HP => Agilent Technologies
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MGA-86563-BLK Datasheet PDF : 8 Pages
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6
RF Layout
The RF layout in Figure 13 is
suggested as a starting point for
amplifier designs using the MGA-
86563 MMIC. Adequate grounding
is needed to obtain maximum
performance and to obviate
potential instability. All four
ground pins of the MMIC should
be connected to RF ground by
using plated through holes (vias)
near the package terminals.
It is recommended that the PCB
pads for the ground pins NOT be
connected together underneath
the body of the package. PCB
traces hidden under the package
cannot be adequately inspected
for SMT solder quality.
PCB Material
FR-4 or G-10 printed circuit board
material is a good choice for most
low cost wireless applications.
Typical board thickness is 0.020
or 0.031 inches. The width of 50 Ω
microstriplines in PC boards of
these thicknesses is also
convenient for mounting chip
components such as the series
inductor that is used at the input
for impedance matching or for
DC blocking capacitors.
For applications requiring the
lowest noise figures, the use of
50 Ω
PTFE/glass dielectric materials
may be warranted to minimize
transmission line losses at the
amplifier input. A 0.5 inch length
of 50 Ω microstripline on FR-4
has approximately 0.3 dB loss at
4 GHz which will add directly to
the noise figure of the
MGA-86563.
Typical Application Circuit
A typical implementation of the
MGA-86563 as a low noise ampli-
fier is shown in Figure 14.
A 50 Ω microstripline with a
series DC blocking capacitor, C1,
is used to feed RF to the MMIC.
The input of the MGA-86563 is
already partially matched for
noise figure and gain to 50 Ω. The
use of a simple input matching
circuit, such as a series inductor,
will minimize amplifier noise
figure. Since the impedance
match for NFO (minimum noise
figure) is very close to a
conjugate power match, a low
noise figure can be realized
simultaneously with a low input
VSWR.
DC power is applied to the MMIC
through the same pin that is
shared with the RF output. A 50 Ω
microstripline is used to connect
the device to the following stage.
A bias decoupling network is used
to feed in Vd while simultan-
eously providing a DC block to
the RF signal. The bias
RF INPUT
86
50 Ω
RF OUTPUT
AND Vd
Vd
C3
decoupling network shown in
Figure 14, consisting of resistor
R1, a short length of high
impedance microstripline, and
bypass capacitor C3, will provide
excellent performance over a
wide frequency range. Surface
mount chip inductors could be
used in place of the high
impedance transmission line to
act as an RF choke. Consideration
should be given to potential
resonances and signal radiation
when using lumped inductors.
For operation at frequencies
below approximately 2 GHz, the
addition of a simple impedance
matching circuit to the output
will increase the gain and output
power by 0.5 to 1.5 dB. The
output matching circuit will not
effect the noise figure.
A small value resistor placed in
series with the Vdd line may be
useful to “de-Q” the bias circuit.
Typical values of R1 are in the
10 Ω to 100 Ω range. Depending
on the value of resistance used,
the supply voltage may have to be
increased to compensate for volt-
age drop across R1. The power
supply should be capacitively
bypassed (C3) to ground to
prevent undesirable gain varia-
tions and to eliminate unwanted
feedback through the bias lines
that could cause oscillation.
Figure 13. RF Layout.
C1
L1
50 Ω
50 Ω
HIGH Z
R1
C2
50 Ω
50 Ω
Figure 14. Typical Amplifier Circuit.
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