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SC28C94C1A

Quad universal asynchronous receiver/transmitter (QUART)

Philips Electronics 

Philips Semiconductors

Quad universal asynchronous receiver/transmitter (QUART)

Product data sheet

SC28C94

Table 1. QUART Registers1

A5:0

READ (RDN = Low)

WRITE (WRN = Low)

000000

Mode Register a (MR0a, MR1a, MR2a)

Mode Register a (MR0a, MR1a, MR2a)

000001

Status Register a (SRa)

Clock Select Register a (CSRa)

000010

Reserved

Command Register a (CRa)

000011

Receive Holding Register a (RxFIFOa)

Transmit Holding Register a (TxFIFOa)

000100

Input Port Change Reg ab (IPCRab)

Auxiliary Control Reg ab (ACRab)

000101

Interrupt Status Reg ab (ISRab)

Interrupt Mask Reg ab (IMRab)

000110

Counter/Timer Upper ab (CTUab)

Counter/Timer Upper Reg ab (CTURab)

000111

Counter/Timer Lower ab (CTLab)

Counter/Timer Lower Reg ab (CTLRab)

001000

Mode Register b (MR0b, MR1b, MR2b)

Mode Register b (MR0b, MR1b, MR2b)

001001

Status Register b (SRb)

Clock Select Register b (CSRb)

001010

Reserved

Command Register b (CRb)

001011

Receive Holding Register b (RxFIFOb)

Transmit Holding Register b (TxFIFOb)

001100

Output Port Register ab (OPRab)

Output Port Register ab (OPRab)

001101

Input Port Register ab (IPRab)

I/OPCRa (I/O Port Control Reg a)

001110

Start Counter ab

I/OPCRb (I/O Port Control Reg b)

001111

Stop Counter ab

Reserved

010000

Mode Register c (MR0c, MR1c, MR2c)

Mode Register c (MR0c, MR1c, MR2c)

010001

Status Register c (SRc)

Clock Select Register c (CSRc)

010010

Reserved

Command Register c (CRc)

010011

Receive Holding Register c (RxFIFOc)

Transmit Holding Register c (TxFIFOc)

010100

Input Port Change Reg cd (IPCRcd)

Auxiliary Control Reg cd (ACRcd)

010101

Interrupt Status Reg cd (ISRcd)

Interrupt Mask Reg cd (IMRcd)

010110

Counter/Timer Upper cd (CTUcd)

Counter/Timer Upper Reg cd (CTURcd)

010111

Counter/Timer Lower cd (CTLcd)

Counter/Timer Lower Reg cd (CTLRcd)

011000

Mode Register d (MR0d, MR1d, MR2d)

Mode Register d (MR0d, MR1d, MR2d)

011001

Status Register d (SRd)

Clock Select Register d (CSRd)

011010

Reserved

Command Register d (CRd)

011011

Receive Holding Register d (RxFIFOd)

Transmit Holding Register d (TxFIFOd)

011100

Output Port Register cd (OPRcd)

Output Port Register cd (OPRcd)

011101

Input Port Register cd (IPRcd)

I/OPCRc (I/O Port Control Reg c)

011110

Start Counter cd

I/OPCRd (I/O Port Control Reg d)

011111

Stop Counter cd

Reserved

100000

Bidding Control Register a (BCRa)

Bidding Control Register a (BCRa)

100001

Bidding Control Register b (BCRb)

Bidding Control Register b (BCRb)

100010

Bidding Control Register c (BCRc)

Bidding Control Register c (BCRc)

100011

Bidding Control Register d (BCRd)

Bidding Control Register d (BCRd)

100100

Reserved

Power Down

100101

Reserved

Power Up

100110

Reserved

Disable DACKN

100111

Reserved

Enable DACKN

101000

Current Interrupt Register (CIR)

Reserved

101001

Global Interrupting Channel Reg (GICR)

Interrupt Vector Register (IVR)

101010

Global Int Byte Count Reg (GIBCR)

Update CIR

101011

Global Receive Holding Reg (GRxFIFO)

Global Transmit Holding Reg (GTxFIFO)

101100

Interrupt Control Register (ICR)

Interrupt Control Register (ICR)

101101

101110

101111

Reserved

Reserved

Reserved

BRG Rate. 00 = low; 01 = high

Set X1/CLK divide by two2 (use when X1 is t 4 Mhz)

Set X1/CLK Normal2

110000–111000 Reserved

Reserved

111001

Reserved

Test Mode

111010–111111 Reserved

Reserved

NOTES:

1. Registers not explicitly reset by hardware reset power up randomly.

2. In X1/CLK divide by 2 all circuits receive the divided clock except the BRG and change-of-state detectors.

2006 Aug 09

6

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