S3C4510B Ver la hoja de datos (PDF) - Samsung

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S3C4510B

Samsungs S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems.

Samsung 

S3C4510B

PRODUCT OVERVIEW

Signal

TXD[3:0]

LOOP_10M

TXD_10M

TX_EN/

TXEN_10M

TX_ERR/

PCOMP_10M

CRS/CRS_10M

RX_CLK/

RXCLK_10M

RXD[3:0]/

RXD_10M

Table 1-1. S3C4510B Signal Descriptions (Continued)

Pin No.

44, 43, 40,

39

47

45

28

37

35, 34, 33,

30

Type

O

O

O

I

I

I

Description

Transmit Data/Transmit Data for 10 M/Loop-back for 10M.

Transmit data is aligned on nibble boundaries. TXD[0]

corresponds to the first bit to be transmitted on the physical

medium, which is the LSB of the first byte and the fifth bit of that

byte during the next clock. TXD_10M is shared with TXD[0] and

is a data line for transmitting to the 10-Mbit/s PHY. LOOP_10M is

shared with TXD[1] and is driven by the loop-back bit in the

control register.

Transmit Enable/Transmit Enable for 10M. TX_EN provides

precise framing for the data carried on TXD[3:0]. This pin is

active during the clock periods in which TXD[3:0] contains valid

data to be transmitted from the preamble stage through CRC.

When the controller is ready to transfer data, it asserts

TXEN_10M.

Transmit Error/Packet Compression Enable for 10M. TX_ERR is

driven synchronously to TX_CLK and sampled continuously by

the Physical Layer Entity, PHY. If asserted for one or more

TX_CLK periods, TX_ERR causes the PHY to emit one or more

symbols which are not part of the valid data, or delimiter set

located somewhere in the frame that is being transmitted.

PCOMP_10M is asserted immediately after the packet's DA field

is received. PCOMP_10M is used with the Management Bus of

the DP83950 Repeater Interface Controller (from National

Semiconductor). The MAC can be programmed to assert

PCOMP if there is a CAM match, or if there is not a match. The

RIC (Repeater Interface Controller) uses this signal to compress

(shorten) the packet received for management purposes and to

reduce memory usage. (See the DP83950 Data Sheet, published

by National Semiconductor, for details on the RIC Management

Bus.). This pin is controlled by a special register, with which you

can define the polarity and assertion method (CAM match active

or not match active) of the PCOMP signal.

Carrier Sense/Carrier Sense for 10M. CRS is asserted

asynchronously with minimum delay from the detection of a non-

idle medium in MII mode. CRS_10M is asserted when a 10-

Mbit/s PHY has data to transfer. A 10-Mbit/s transmission also

uses this signal.

Receive Clock/Receive Clock for 10M. RX_CLK is a continuous

clock signal. Its frequency is 25 MHz for 100-Mbit/s operation,

and 2.5 MHz for 10-Mbit/s. RXD[3:0], RX_DV, and RX_ERR are

driven by the PHY off the falling edge of RX_CLK, and sampled

on the rising edge of RX_CLK. To receive data, the TXCLK_10 M

clock comes from the 10-Mbit/s PHY.

Receive Data/Receive Data for 10M. RXD is aligned on nibble

boundaries. RXD[0] corresponds to the first bit received on the

physical medium, which is the LSB of the byte in one clock

period and the fifth bit of that byte in the next clock. RXD_10M is

shared with RXD[0] and it is a line for receiving data from the 10-

Mbit/s PHY.

1-9

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