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S3C4510B Ver la hoja de datos (PDF) - Samsung

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S3C4510B Datasheet PDF : 422 Pages
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PRODUCT OVERVIEW
S3C4510B
SCL
SDA
18 I/O Ports including
4: Ext INT req.
2: Timer out (0,1)
2: Ext DMA REQ.
2: Ext DMA ACK
Console
Xtal OSC
ARM7TDMI
32-bit RISE CPU
ICE-
Breaker
CPU Interface
8-Kbyte
Unified
Cache
32-Bit
Sytem
Bus
Memory
Controller
with
Refresh
Control
4-Word
Write
Buffer
Bus Rounter
I2C
18 General I/O ports
Interruput Controller
UART 0,1
32-bit Timer 0,1
GDMA 0,1
PLL
System
Bus
Arbiter
Ext Bus
REQ/ACK
2-Channel HDLCs
with DMAs
Ethernet Controller
2-channel BDMA
BDMA RAMs
Tx Buffer (256 bytes)
Rx Buffer (256 bytes)
CAM (128 bytes)
MAC
Tx FIFO (80 bytes)
Rx FIFO (16 bytes)
TAP Controller for JTAG
6-bank
ROM
SRAM
FLASH
4-bank
DRAM
4-bank
External
I/O
Device
External
Bus
Master
Remote
port A,B
MII or
7-wire
Figure 1-1. S3C4510B Block Diagram
1-4

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