S39421 Ver la hoja de datos (PDF) - Summit Microelectronics

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S39421

Hot Swap Voltage Controller

Summit Microelectronics 

S39421

DEVICE OPERATION

Power-Up Sequence

A sequencing operation is initiated by the physical inser-

tion of the card into the platform’s connector. The

S39421’s VCC5 pin should be connected to the early

power pins of the connector. As soon as power is applied,

the S39421 will drive the reset outputs active and clamp

the VGATE outputs to ground.

Proper card insertion is insured by detecting the presence

of a low level on the pin detect (PND1, PND2) inputs,

which should be located on opposite ends of the bus

connector. These pin detect inputs have internal pull-up

resistors and the connection on the host platform side

must be connected directly to ground. [In a CompactPCI

application these are the BD_SEL# signals]. The PND

inputs have an internal noise filter nominally set at 150ms.

Once the proper card insertion has been detected, the

S39421 will check the status of the HST_PWR signal from

the host.

RESET CONTROL

In order to provide positive control to an add-in-card’s

bakckend logic, the reset control function of the S39421

begins operation as soon as a voltage is applied to VCC5.

The conditions that affect the reset outputs are the VCC5,

VCC3, CARD_5V and CARD_3V input levels and the

state of the HST_RST input.

Assume HST_RST has been released and is pulled high.

The S39421 reset ouputs will be valid as long as VCC5

is • 1V. If any one of VCC5, VCC3, CARD_5V or

CARD_3V input levels is below its respective Vtrip level

the reset outputs and CARD_V_VLD output will be driven

active. (In the case of the CARD_V_VLD output, the

active condition is low but its logical true condition is a

release of its open drain output pulled high by an external

pull-up) As soon as the VCC5, VCC3, CARD_5V and

CARD_3V inputs are above their Vtrip levels

CARD_V_VLD will be released and the internal tPURST

timer will be started. The reset outputs will be held active

until tPURST has expired and then be released.

Implementation of HST_PWR is optional; e.g. it can be

used to power down individual cards on the bus via

software control. If it is not used by the host system the

input must be held high in order for the S39421 to enable

power sequencing to the card.

Once these basic conditions are met the S39421 will

begin the power-up portion of the sequence. First, the

host platform supplies are checked for compliance.

Based on the state of the VSEL input the S39421 will

monitor the +5V and +3.3V supplies. If these are above

the VTRIP thresholds the sequencing next begins the

backend logic power-on operation.

The S39421 will drive the VGATE3 and VGATE5 outputs

to the 12V rail to turn on the external 3 volt and 5 volt power

FETs. The slew rate of these outputs defaults to 250V/s.

Different slew rates can be accommodated by either

adding an additional capacitor between the FET gate and

ground or by injecting current into the ISLEW input.

The HST_RST input is also used to control the reset

outputs. A high to low transition on HST_RST will initiate

a reset cycle with a duration of tPURST. The reset outputs

will remain active for a minimum period tPURST or for the

duration of HST_RST active low, whichever is longer. A

HST_RST activated reset will not affect the power se-

quencing logic.

During normal operation, the supply voltages are continu-

ously monitored. If the cardside supplies fall below the

VTRIP levels the reset outputs will be driven active. If the

host platform supplies fall below VTRIP, the S39421 will

immediately assert the reset outputs and disable the

highside drivers.

Power Configurations

The S39421 can be used in 5V-only, 3.3V-only and mixed

voltage systems. For mixed voltage systems, simply

connect the appropriate bus and card power inputs as

indicated. The VSEL pin should be grounded.

For systems with a single power supply, connect VCC5

and VCC3 together to the platform host early power line

(long pin power supply). Also connect CARD5V and

CARD3V together to the cardside power output of the

FET.

The state of VSEL determines the reset level that will be

used to signal CARD_V_VLD. For 3.3V systems, tie

VSEL to the supply; for 5V systems, tie VSEL to ground.

2024 9.0 8/8/00

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