74LVCH162374ADL Ver la hoja de datos (PDF) - Philips Electronics

Número de pieza

componentes Descripción

Fabricante

74LVCH162374ADL

16-bit edge triggered D-type flip-flop with 30 Ω series termination resistors; 5 V input/output tolerant; 3-state

Philips Electronics 

Philips Semiconductors

Product specification

16-bit edge triggered D-type flip-flop with 30 Ω series 74LVC162374A;

termination resistors; 5 V input/output tolerant; 3-state 74LVCH162374A

FEATURES

• ESD protection:

HBM EIA/JESD22-A114-A

exceeds 2000 V

MM EIA/JESD22-A115-A

exceeds 200 V

• 5 V tolerant input/output for

interfacing with 5 V logic

• Wide supply voltage range of

1.2 to 3.6 V

• Complies with JEDEC standard

no. 8-1A

• CMOS low power consumption

• MULTIBYTE™ flow-through

standard pin-out architecture

• Low inductance multiple power and

ground pins for minimum noise and

ground bounce

• Direct interface with TTL levels

• All data inputs have bus hold

(74LVCH162374A only)

• High impedance when VCC = 0

• Power off disables outputs,

permitting live insertion.

DESCRIPTION

The 74LVC(H)162374A is a 16-bit edge triggered flip-flop featuring separate

D-type inputs for each flip-flop and 3-state outputs for bus oriented applications.

The 74LVC162374A consists of 2 sections of eight edge-triggered flip-flops.

A clock (CP) input and an output enable (OE) are provided for each octal.

Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation,

outputs can handle 5 V. These features allow the use of these devices in a

mixed 3.3 and 5 V environment.

The flip-flops will store the state of their individual D-inputs that meet the set-up

and hold time requirements on the LOW-to-HIGH CP transition.

When OE is LOW, the contents of the flip-flops are available at the outputs.

When OE is HIGH, the outputs go to the high-impedance OFF-state.

Operation of the OE input does not affect the state of the flip-flops.

The 74LVCH162374A bus hold data inputs eliminates the need for external pull

up resistors to hold unused inputs.

The 74LVC(H)162374A is designed with 30 Ω series termination resistors in

both HIGH and LOW output stages to reduce line noise.

FUNCTION TABLE

See note 1.

OPERATION MODES

Load and read register

Latch register and disable outputs

INPUTS

nOE

nCP

nDn

L

↑

l

L

↑

h

H

↑

l

H

↑

h

Note

1. H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;

Z = high-impedance OFF-state;

↑ = LOW-to-HIGH CP transition.

INTERNAL

FLIP-FLOPS

L

H

L

H

OUTPUTS

Q0 to Q7

L

H

Z

Z

1999 Aug 05

2

Share Link: