PCD5002 Ver la hoja de datos (PDF) - Philips Electronics

Número de pieza

componentes Descripción

Fabricante

PCD5002

Advanced POCSAG and APOC-1 Paging Decoder

Philips Electronics 

Philips Semiconductors

Advanced POCSAG and APOC-1 Paging

Decoder

Product specification

PCD5002

1 FEATURES

• Wide operating supply voltage range: 1.5 to 6.0 V

• EEPROM programming requires only 2.0 V supply

• Low operating current: 50 µA typ. (ON), 25 µA typ.

(OFF)

• Temperature range −25 to +70 °C

• “CCIR radio paging Code No. 1” (POCSAG) compatible

• Supports Advanced Pager Operator’s Code Phase 1

(APOC-1) for extended battery economy

• 512, 1200 and 2400 bits/s data rates using 76.8 kHz

crystal

• Built-in data filter (16-times oversampling) and bit clock

recovery

• Advanced ACCESS® synchronization algorithm

• 2-bit random and (optional) 4-bit burst error correction

• Up to 6 user addresses (RICs), each with

4 functions/alert cadences

• Up to 6 user address frames, independently

programmable

• Standard POCSAG sync word, plus up to 4 user

programmable sync words

• Continuous data decoding upon reception of user

programmable sync word (optional)

• Received data inversion (optional)

• Call alert via beeper, vibrator or LED

• 2-level acoustic alert using single external transistor

• Alert control: automatic (POCSAG type), via cadence

register or alert input pin

• Separate power control of receiver and RF oscillator for

battery economy

• Synthesizer set-up and control interface (3-line serial)

• On-chip EEPROM for storage of user addresses (RICs),

pager configuration and synthesizer data

• On-chip SRAM buffer for message data

• Slave I2C-bus interface to microcontroller for transfer of

message data, status/control and EEPROM

programming (data transfer at up to 100 kbits/s)

• Wake-up interrupt for microcontroller, programmable

polarity

• Direct and I2C-bus control of operating status (ON/OFF)

• Battery-low indication (external detector)

• Out-of-range condition indication

• Real time clock reference output

• On-chip voltage doubler

• Interfaces directly to UAA2080 and UAA2082 paging

receivers.

2 APPLICATIONS

• Advanced display pagers (POCSAG and APOC-1)

• Basic alert-only pagers

• Information services

• Personal organizers

• Telepoint

• Telemetry/data transmission.

3 GENERAL DESCRIPTION

The PCD5002 is a very low power pager decoder and

controller, capable of handling both standard POCSAG

and the advanced APOC-1 code. Continuous data

decoding upon reception of a dedicated sync word is

available for news pager applications.

Data rates supported are 512, 1200 and 2400 bits/s using

a single 76.8 kHz crystal. On-chip EEPROM is

programmable using a minimum supply voltage of 2.0 V,

allowing ‘over-the-air’ programming. I2C-bus compatible.

4 ORDERING INFORMATION

TYPE

NUMBER

NAME

PACKAGE

DESCRIPTION

PCD5002H LQFP32 plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm

PCD5002U/10

− film-frame carrier (naked die) 32 pads

VERSION

SOT358-1

−

5 LICENSE

Supply of this IC does neither convey nor express an implied license under any patent right to use this in any APOC

application.

1997 Jun 24

3

Share Link: