OR2C04A Ver la hoja de datos (PDF) - Lattice Semiconductor

Número de pieza

componentes Descripción

Fabricante

OR2C04A

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

ORCA Series 2 FPGAs

Data Sheet

January 2002

Clock Distribution Network (continued)

Secondary Clock

CLK PIN

SEE DETAIL A

SEE DETAIL B

There are times when a primary clock is either not

available or not desired, and a secondary clock is

needed. For example:

■ Only one input pad per PIC can be placed on the

clock routing. If a second input pad in a given PIC

requires global signal routing, a secondary clock

route must be used.

CLOCK

BRANCHES

■ Since there is only one branch driver in each PLC for

either direction (vertical and horizontal), both clock

lines in a particular row or column (CKL and CKR, for

example) cannot drive a branch. Therefore, two

clocks should not be placed into I/O pads in PICs on

the opposite sides of the same row or column if glo-

bal clocks are to be used.

CLOCK SPINE

PIC PT8

A

B

C

D

DT

DT

DT

DT

PLC R1C8

■ Since the clock lines can only be driven from input

pads, internally generated clocks should use second-

ary clock routing.

Figure 35 illustrates the secondary clock distribution. If

the clock signal originates from either the left or right

side of the FPGA, it can be routed through the TRIDI

buffers in the PIC onto one of the adjacent PLC’s hori-

zontal XL lines. If the clock signal originates from the

top or bottom of the FPGA, the vertical XL lines are

used for routing. In either case, an XL line is used as

the clock spine. In the same manner, if a clock is only

going to be used in one quadrant, the XH lines can be

used as a clock spine. The routing of the clock spine

from the input pads to the VXL (VXH) using the BIDIs

(BIDIHs) is shown in Figure 35, Detail A.

HCK

PLC R18C8

DETAIL A

HCK

CLOCK SPINE

CKT

In each PLC, a low-skew connection through a long-

line driver can be used to connect a horizontal XL line

to a vertical XL line or vice versa. As shown in Figure

35, Detail B, this is used to route the branches from the

clock spine. If the clock spine is a vertical XL line, then

the branches are horizontal XL lines and vice versa.

The clock is then routed into each PLC from the XL line

clock branches.

R7C7

R7C8

HXL

HXL

CLOCK

BRANCH

CLOCK

SPINES

DETAIL B

CKB CKT

To minimize skew, the PLC clock input for all PLCs

must be connected to the branch XL lines, not the

spine XL line. Even in PLCs where the clock is routed

from the spine to the branches, the clock should be

routed back into the PLC from the clock branch.

If the clock is to drive only a limited number of loads,

the PFUs can be connected directly to the clock spine.

In this case, all flip-flops driven by the clock must be

located in the same row or column.

5-4480(F).r3

Figure 34. Primary Clock Distribution

38

Lattice Semiconductor

Share Link: