NIS5101 Ver la hoja de datos (PDF) - ON Semiconductor
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NIS5101 Datasheet PDF : 12 Pages
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NIS5101
OPERATION DESCRIPTION
Turn−on
The SMART HotPlug monitors the input voltage by
sensing the voltage across the Input + to Input − pins. When
the UVLO voltage has been reached, the internal circuitry
slowly charges the gate of the internal SENSEFET™.
There will be a slight delay of several milliseconds before
the SENSEFET begins conduction. This may be increased
by adding a capacitor to the UVLO pin. For a discussion of
this, see application note AND8115/D.
The SENSEFET will increase the load current with a
controlled di/dt until the current limit level has been
reached. At this point the SENSEFET will enter a constant
current mode of operation until the load capacitor has been
fully charged. If the thermal limit threshold is reached
before the capacitor reaches its final charge level, the
device will shut down until the die temperature reaches
95°C and then restart, if it is the auto−retry device. The
thermal latching version must not be allowed to reach the
thermal shutdown level at turn−on as this will cause it to
latch in an off state.
During the capacitor charging period, the dv/dt of the
capacitor is:
dvńdt
+
ILIMIT
CLOAD
Faults
Once the load capacitance is charged, the SENSEFET
will become fully enhanced as long as the current does not
reach the current limit threshold, or is shut−down due to an
overvoltage, undervoltage or thermal fault. Both the
UVLO and OVLO circuits incorporate hysteresis to assure
clean turn−on and turn−offs with no chatter. The thermal
latching circuit will require the input power to be recycled
to resume operation after a fault. The current limit is always
active, so any transient or overload will always be limited.
Circuit Description
Undervoltage Lockout: The UVLO circuit holds the chip
off when the input voltage is less than the turn−on limit. It
includes internal hysteresis to assure clean on/off
switching. An internal divider sets the turn−on voltage
level at 46 V. This voltage can be reduced by adding an
external resistor from the UVLO pin to the Input + pin. The
equivalent circuit is shown in Figure 17.
Input +
UVLO/
ENABLE
RUVLO
200 k
100 k
Vreg
12.5 V
Vz
ZD1
Drain
50 k
Input −
Figure 17. Undervoltage Lockout Circuit
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