MX98745 Ver la hoja de datos (PDF) - Macronix International
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MX98745 Datasheet PDF : 36 Pages
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MX98745
C. Universal Port (UP), 14 pins
PAD # Name
43
SIGDET0/
RXDV
44-47 RDAT0[0:3]/
RXD[0:3]
48
RDAT04/
RXER
56
CRS
57
TXEN
49-52 TDAT[0:3]/
TXD[0:3]
53
TDAT04/
TXER
37
COL
54
TXCLK
I/O
I,
TTL
I,
TTL
I,
TTL
I/O,
TTL
O,
CMOS
O,
CMOS
O,
CMOS
I/O,
CMOS
I/O,
CMOS
Description
Signal Detect/Receive Data Valid. When TXMII (pin 84) is detected high
during power on reset, This pin works as Signal detect in 5B data mode. When
TXMII is low, this pin is output and works as RXDV in MII mode. This signal
remains asserted through the whole frame, starting with the start-of-frame
delimiter and excluding any end-of-frame deliminter
Receive Data[3:0]. No matter TXMII’s value is, these four pins work as the
receive data both in TX mode and MII mode. Receive data is synchronous to
RSCLK0's rising edge.
Receive Data Bit 4/Receive Data Error. When TXMII is detected as 1, this pin
works as the MSB of RDAT0[4:0]. When MII mode is selected, this pin is
RXER and synchronous to RSCLK0's rising edge.
Carrier Sense. In PCS Mode, synchronous to TXCLK. This pin is asserted
when (1) the receiving medium is not idle, or (2) the transmitting medium is not
idle in the half-duplex mode. In MAC mode (PMSEL is low), this pin is input.
Transmit Enable. This pin is output and synchronous to the TXCLK's rising
edge whenever valid data is presented on TXD[3:0]
Transmit Data. No matter TXMII’s value is, these four pins work as the
transmit data both in TX mode and MII mode. In TX mode, TDAT is
synchronous to LSCLK rising edge. In MII mode, TXD[0:3] is synchronous to
TXCLK rising edge.
Transmit Data Bit 4/Transmit ERROR. When TXMII is set to one, this pin work
as the MSB of TDAT of port 0. When TXMII is low, This pin acts as TXEN and
is synchronous to the TXCLK's rising edge. When TXER is asserted for one or
more than one TXCLK period while TXEN is also asserted, one or more"HALT ”
symbols will present at TXD[3:0].
Collision. This signal is asserted if both the receiving media and TXEN are
active. When PCS type MII is selected, this pin is output from XRCII and
indicates that there is collision within the XRCII. When PMSEL is 0, COL is
input to XRCII and indicates that there is collision on the receiving port.
Transmit Clock. 25M Hz clock. TXD[3:0], TXEN, TXER are synchronous to
this clock's rising edge. In PCS type MII (PMSEL is 1), CRS and COL are also
synchronous to this clock's rising edge.
Table 5-1 Pin Description for XRCII (Continued)
P/N:PM0427
REV. 1.4, JUL. 8, 1998
6
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