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MX28F1000P

1M-BIT [128K x 8] CMOS FLASH MEMORY

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MX28F1000P

The MX28F1000P applies an internally generated

margin voltage to the addressed byte. Reading FFH

from the addressed byte indicates that all bits in the

byte are erased.

The erase-verify command must be written to the

command register prior to each byte verification to

latch its address. The process continues for each byte

in the array until a byte does not return FFH data, or the

last address is accessed.

In the case where the data read is not FFH, another

erase operation is performed. (Refer to Set-up Erase/

Erase). Verification then resumes from the address of

the last-verified byte. Once all bytes in the array have

been verified, the erase step is complete. The device

can be programmed. At this point, the verify operation

is terminated by writing a valid command (e.g.

Program Set-up) to the command register. The High

Reliability Erase algorithm, illustrates how commands

and bus operations are combined to perform electrical

erasure of the MX28F1000P.

RESET COMMAND

A reset command is provided as a means to safely

abort the erase- or program-command sequences.

Following either set-up command (erase or program)

with two consecutive writes of FFH will safely abort the

operation. Memory contents will not be altered.

Should program-fail or erase-fail happen, two

consecutive writes of FFH will reset the device to abort

the operation. A valid command must then be written

to place the device in the desired state.

WRITE OPERATON STATUS

TOGGLE BIT-DQ6

The MX28F1000P features a "Toggle Bit" as a method

to indicate to the host sytem that the Auto Program/

Erase algorithms are either in progress or completed.

While the Automatic Program or Erase algorithm is in

progress, successive attempts to read data from the

device will result in DQ6 toggling between one and

zero. Once the Automatic Program or Erase algorithm

is completed, DQ6 will stop toggling and valid data will

be read. The toggle bit is valid after the rising edge of

the second WE pulse of the two write pulse

sequences.

DATA POLLING-DQ7

The MX28F1000P also features Data Polling as a

method to indicate to the host system that the

Automatic Program or Erase algorithms are either in

progress or completed.

While the Automatic Programming algorithm is in op-

eration, an attempt to read the device will produce the

complement data of the data last written to DQ7. Upon

completion of the Automatic Program algorithm an

attempt to read the device will produce the true data

last written to DQ7. The Data Polling feature is valid

after the rising edge of the second WE pulse of the two

write pulse sequences.

While the Automatic Erase algorithm is in operation,

DQ7 will read "0" until the erase operation is com-

pleted. Upon completion of the erase operation, the

data on DQ7 will read "1". The Data Polling feature is

valid after the rising edge of the second WE pulse of

two write pulse sequences.

The Data Polling feature is active during Automatic

Program/Erase algorithms.

POWER-UP SEQUENCE

The MX28F1000P powers up in the Read only mode. In

addition, the memory contents may only be altered after

successful completion of a two-step command sequence.

Power up sequence is not required.

SYSTEM CONSIDERATIONS

During the switch between active and standby condi-

tions, transient current peaks are produced on the

rising and falling edges of Chip Enable. The magnitude

of these transient current peaks is dependent on the

output capacitance loading of the device. At a

minimum, a 0.1uF ceramic capacitor (high frequency,

low inherent inductance) should be used on each

device between VCC and GND, and between VPP and

GND to minimize transient effects. In addition, to

overcome the voltage drop caused by the inductive

effects of the printed circuit board traces on FLASH

memory arrays, a 4.7uF bulk electrolytic capacitor

should be used between VCC and GND for each eight

devices. The location of the capacitor should be close

to where the power supply is connected to the array.

P/N: PM0340

REV. 1.6, JAN. 19, 1999

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