MX25L4005M2C-15 Ver la hoja de datos (PDF) - Macronix International

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MX25L4005M2C-15

4M-BIT [x 1] CMOS SERIAL FLASH

Macronix International 

MX25L4005

DEVICE OPERATION

1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.

2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until

next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.

3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next

CS# rising edge.

4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The

difference of SPI mode 0 and mode 3 is shown as Figure 2.

Figure 2. SPI Modes Supported

CPOL CPHA

(SPI mode 0) 0

0

SCLK

(SPI mode 3) 1

1

SCLK

SI

SO

MSB

MSB

5. For the following instructions: RDID, RDSR, READ, FAST_READ, RES and REMS the shifted-in instruction sequence

is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following

instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP and DP the CS# must go high exactly at the byte boundary;

otherwise, the instruction will be rejected and not executed.

6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and

not affect the current operation of Write Status Register, Program, Erase.

P/N: PM1236

REV. 1.1, SEP. 30, 2005

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