MT48LC32M8A2P-6ALD(2007) Ver la hoja de datos (PDF) - Micron Technology
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MT48LC32M8A2P-6ALD Datasheet PDF : 77 Pages
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256Mb: x4, x8, x16 SDRAM
Features
Synchronous DRAM
MT48LC64M4A2 – 16 Meg x 4 x 4 banks
MT48LC32M8A2 – 8 Meg x 8 x 4 banks
MT48LC16M16A2 – 4 Meg x 16 x 4 banks
For the latest data sheet, refer to Micron’s Web site: www.micron.com
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge,
and auto refresh modes
• Self refresh mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
Table 1: Address Table
Parameter 64 Meg x 4 32 Meg x 8 16 Meg x 16
Configuration
Refresh count
Row
addressing
Bank
addressing
Column
addressing
16 Meg x 4
x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
2K (A0–A9,
A11)
8 Meg x 8
x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
1K (A0–A9)
4 Meg x 16
x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
512 (A0–A8)
Table 2:
Key Timing Parameters
CL = CAS (READ) latency
Speed
Grade
-6A
-7E
-75
-7E
-75
Access Time
Clock
Frequency CL = 2 CL = 3
167 MHz
143 MHz
133 MHz
133 MHz
100 MHz
–
–
–
5.4ns
6ns
5.4ns
5.4ns
5.4ns
–
–
Setup
Time
1.5ns
1.5ns
1.5ns
1.5ns
1.5ns
Hold
Time
0.8ns
0.8ns
0.8ns
0.8ns
0.8ns
Part Number Example:
MT48LC16M16A2TG-75:D
Options
Marking
• Configurations
– 64 Meg x 4 (16 Meg x 4 x 4 banks)
64M4
– 32 Meg x 8 (8 Meg x 8 x 4 banks)
32M8
– 16 Meg x 16 (4 Meg x 16 x 4 banks)
• Write recovery (tWR)
– tWR = “2 CLK”1
• Plastic package – OCPL2
– 54-pin TSOP II OCPL2 (400 mil)
16M16
A2
TG
(standard)
– 54-pin TSOP II OCPL2 (400 mil)
P
Pb-free
– 60-ball FBGA (x4, x8) (8mm x 16mm)
FB
– 60-ball FBGA (x4, x8) Pb-free
BB
(8mm x 16mm)
– 54-ball VFBGA (x16) (8mm x 14 mm)
FG
– 54-ball VFBGA (x16) Pb-free
BG
(8mm x 14 mm)
• Timing (cycle time)
– 6.0ns @ CL = 3 (x8, x16 only)
-6A
– 7.5ns @ CL = 3 (PC133)
-75
– 7.5ns @ CL = 2 (PC133)
-7E
• Self refresh
– Standard
– Low power
None
L3
• Operating temperature range
– Commercial (0°C to +70°C)
None
– Industrial (–40°C to +85°C)
IT
• Design revision
:D
Notes: 1. Refer to Micron technical note: TN-48-05.
2. Off-center parting line.
3. Contact Micron for availability.
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_1.fm - Rev. L 10/07 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
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