MT28F1284W18 Ver la hoja de datos (PDF) - Micron Technology
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MT28F1284W18 Datasheet PDF : 66 Pages
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
General Description
The MT28F1284W18 is a high-performance, high-
density, nonvolatile memory solution that can signifi-
cantly improve system performance. This architecture
features a multipartition configuration that supports
READ-While-PROGRAM/ERASE operations with no
latency. An 8Mb partition size enables optimal design
flexibility.
A high-performance bus interface enables a fast
burst mode READ operation; a conventional asynchro-
nous/page bus interface is provided as well. The burst
interface increases the data throughput, minimizing
the impact of the first data latency.
The MT28F1284W18 enables soft protection for
blocks, as read only, by configuring soft protection reg-
isters with dedicated command sequences. For secu-
rity purposes, two 64-bit chip protection registers are
provided.
The embedded WORD PROGRAM and BLOCK
ERASE functions are fully automated by an on-chip
write state machine (WSM). An on-chip device status
register can be used to monitor the WSM status and
determine the progress of the PROGRAM/ERASE tasks.
Please refer to Micron’s Web site at
www.micron.com/flash for the latest data sheet.
Architecture and Memory Organization
The MT28F1284W18 Flash device contains 16 sepa-
rate partitions (banks) of memory for simultaneous
READ and PROGRAM/ERASE operations. Burst READs
can cross partition boundaries, but the user must
ensure that the burst does not extend into a partition
that is actively programming or erasing. During a PRO-
GRAM/ERASE operation, any of the fifteen other parti-
tions may be read. Note that only two partitions can
operate simultaneously. Partitions are configured as
follows:
• Partition 0 (bottom boot) or partition 15 (top
boot) contains eight 8K-word parameter blocks
and seven 64K-word main blocks.
• The other 15 partitions contain eight 64K-word
main blocks and comprise one-sixteenth of the
total memory.
Figure 3 depicts the memory organization.
Figure 2: Functional Block Diagram
RST#
CE#
WE#
OE#
DQ0–DQ15
Data Input
Buffer
CSM
Data
Register
PR Lock
Query
OTP
Manufacturer’s ID
Device ID
Block Lock
RCR
Status
Reg.
WSM
I/O Logic
Program/
Erase
Pump Voltage
Generators
Output
Multiplexer
DQ0–DQ15
Output
Buffer
A0–A22
ADV#
CLK
Address
Input
Buffer
Address
CNT WSM
Address Latch
BSM
Address
Multiplexer
Y/Z DEC
X DEC
"
"
Y/Z DEC
X DEC
Y/Z Gating/Sensing
Bank 0 Blocks
"
"
Y/Z Gating/Sensing
Bank 15 Blocks
WAIT#
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
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