MT28F1284W18BQ-705BET Ver la hoja de datos (PDF) - Micron Technology
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MT28F1284W18BQ-705BET Datasheet PDF : 66 Pages
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 6: Command Codes and Descriptions (continued)
OPERATION
BLOCK LOCKING
PROTECTION
PROGRAM
SET READ
CONFIGURATION
REGISTER
CODE
DEVICE
MODE
60h Block Lock
Setup
01h Lock Block
D0h Unlock Block
2Fh Lock Down
Block
C0h Protection
Register
Program
Setup
60h Set Read
Configuration
Register Setup
03h Set Read
Configuration
Register Data
BUS
CYCLE
DESCRIPTION
First Prepares the CSM for changes to the block locking status. See note 1.
Second
Second
Second
First
First
If the previous command was BLOCK LOCK SETUP, the CSM will latch
the address and lock the block indicated on the address bus.
If the previous command was BLOCK LOCK SETUP, the CSM will latch
the address and unlock the block indicated on the address bus. If the
block had been previously set to lock down, this operation will have
no effect unless WP# is driven to VIH.
If the previous command was BLOCK LOCK SETUP, the CSM will latch
the address and lock down the block indicated on the address bus.
Prepares the CSM for a PROTECTION REGISTER PROGRAM operation.
The second cycle latches address and data, and starts the WSM’s
protection register program or lock algorithm. After the second
cycle, the device outputs status register data on the falling edge of
OE# or CE#, whichever occurs last. To read array data after
programming, issue a READ ARRAY command.
Prepares the RCR to be modified. See note 1.
Second If the previous command was SET READ CONFIGURATION REGISTER
SETUP, the configuration bits presented on the address bus will be
stored into the Read Configuration Register.
NOTE:
1. If the 60h command is not followed by D0h, 01h, 2Fh, or 03h, the CSM sets SR4 and SR5 to indicate a command
sequence error.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
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