MT28F1284W18 Ver la hoja de datos (PDF) - Micron Technology
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MT28F1284W18 Datasheet PDF : 66 Pages
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Command State Machine (CSM)
Commands are issued to the command state
machine (CSM) using standard microprocessor write
timings. The CSM acts as an interface between exter-
nal microprocessors and the internal write state
machine (WSM). Table 5 defines the available com-
mands and provides data for each of the bus cycles,
and Table 6 provides the command descriptions. Pro-
gram and erase algorithms are automated by an on-
chip WSM. During a PROGRAM or ERASE cycle, the
CSM informs the WSM that a PROGRAM or ERASE
cycle has been requested. Table 27 shows the CSM
transition states.
Once a valid PROGRAM/ERASE command is
entered, the WSM executes the appropriate algorithm,
which generates the necessary timing signals to con-
trol the device internally to accomplish the requested
operation. A command is valid only if the exact
sequence is completed. After the WSM completes its
task, the WSM status bit (SR7) (see Table 7) is set to a
logic HIGH level (VIH), allowing the CSM to respond to
the full command set again.
Command State Machine Activation
Device operations are selected by entering an 8-bit
command code with conventional microprocessor
timings into an on-chip CSM through I/Os DQ0–DQ7.
The number of bus cycles required to activate a com-
mand is typically one or two. The first operation is
always a WRITE. Control signals CE# and WE# must be
at a logic LOW level (VIL), and OE# and RST# must be
at logic HIGH (VIH). The second operation, when
needed, can be a WRITE or a READ, depending upon
the command. During a READ operation, control sig-
nals CE#, ADV#, and OE# must be at a logic LOW level
(VIL), and WE# and RST# must be at logic HIGH (VIH).
Table 4 illustrates the bus operations for all the modes:
write, read, reset, standby, and output disable.
When the device is reset, internal reset circuitry ini-
tializes the chip to a read array mode of operation.
Changing the mode of operation requires that a com-
mand code be entered into the CSM. Users can verify
the status of the operations initiated by the CSM by
reading the status register. This single status register
permits monitoring of the progress of the various
operations that can take place on a memory partition.
Status register bits SR0–SR7 correspond to DQ0–DQ7
(see Table 7).
Table 4: Bus Operations
MODE
Read (array, status registers, device
identifier, or query)
Standby
Output disable
Reset
Write
RST#
VIH
VIH
VIH
VIL
VIH
CE#
VIL
VIH
VIL
X
VIL
ADV#
VIL
X
X
X
X
OE#
VIL
X
VIH
X
VIH
WE#
VIH
X
VIH
X
VIL
WAIT# DQ0–DQ15
Active1
DOUT
High-Z
Active1
High-Z
High-Z
High-Z
High-Z
High-Z
DIN
NOTE:
1. The WAIT# signal is driven by CE#; polarity depends on RCR10. Valid only in synchronous mode only.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
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