T35L6432A Ver la hoja de datos (PDF) - Taiwan Memory Technology
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T35L6432A Datasheet PDF : 15 Pages
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T35L6432A
AC TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
0V to 3.0V
1.5ns
1.5V
1.5V
See Figures 1 and 2
Notes:
1. All voltages referenced to VSS (GND).
2. Overshoot: VIH ≤ +3.6 V for t ≤ tKC/2.
Undershoot: VIL ≤ -1.0 V for t ≤ tKC/2.
3. Icc is given with no output current. Icc increases
with greater output loading and faster cycle
times.
4. This parameter is sampled.
5. Test conditions as specified with the output
loading as shown in Fig. 1 unless otherwise
noted.
6. Output loading is specified with CL = 5 pF as in
Fig. 2.
7. At any given temperature and voltage condition,
tKQHZ is less than tKQLZ and tOEHZ is less
than tOELZ.
8. A READ cycle is defined by byte write enables
all HIGH or ADSP LOW along with chip
enables being active for the required setup and
hold times. A WRITE cycle is defined by at one
byte or all byte WRITE per READ/WRITE
TRUTH TABLE.
9. OE is a "don't care" when a byte write enable is
sampled LOW.
10.This is a synchronous device. All synchronous
inputs must meet specified setup and hold time,
except for "don't care" as defined in the truth
table.
11.AC I/O curves are available upon request.
12."Device Deselected means the device is in
POWER-DOWN mode as defined in the truth
table. "Device Selected" means the device is
active.
13.Typical values are measured at 3.3V, 25°C and
20ns cycle time.
14.MODE pin has an internal pull-up and exhibits
an input leakage current of ± 10µA.
OUTPUT LOADS
DQ
Z0 = 50
50
Vt = 1.5V
30 pF
Fig.1 OUTPUT LOAD EQUIVALENT
3.3V
DQ
351
317
5 pF
Fig.2 OUTPUT LOAD EQUIVALENT
Taiwan Memory Technology, Inc. reserves the right P. 9
to change products or specifications without notice.
Publication Date: DEC. 1998
Revision:A
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