MK1573-02S Ver la hoja de datos (PDF) - Integrated Circuit Systems

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MK1573-02S

GenClock™ HSYNC to Video Clock

Integrated Circuit Systems 

MK1573-02

GenClock™ HSYNC to Video Clock

Clock Waveforms

In addition to generating the video clock on CLK1 (pin 10), the MK1573 also outputs the recovered

HSYNC clocks. On certain selections, a double speed recovered HSYNC clock is also available. These

recovered clocks will have lower jitter than the HSYNC input due to the filtering action of the PLL. The

jitter spectrum of the recovered clocks will be reduced at frequencies higher than the loop bandwidth. The

above section describes how to calculate the approximate loop bandwidth. The waveforms of the

recovered clocks fall into one of three different groups depending on the address selection:

Addresses 0 to 7 and C

HSYNC

input

CLK3

Addresses A and B

HSYNC

input

CLK2

CLK3

Addresses D, E, and F

HSYNC

input

CLK2

CLK3

The recovered clocks are triggered by the falling edge of HSYNC and are delayed by about 100ns.

MDS 1573-02 B

5

Revision 120497

Printed 11/15/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•www.icst.com

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