MK1573-02S Ver la hoja de datos (PDF) - Integrated Circuit Systems

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MK1573-02S

GenClock™ HSYNC to Video Clock

Integrated Circuit Systems 

MK1573-02

GenClock™ HSYNC to Video Clock

External Components/Crystal Selection

The MK1573 requires a minimum number of external components for proper operation. A 0.1µF low

leakage capacitor (see Capacitor Selection on following page) should be connected between CAP1 and

CAP2 as close to the chip as possible. A high quality ceramic capacitor is recommended. A decoupling

capacitor of 0.1µF must be connected between VDD and GND pins (pins 2 and 3, 5 and 7) close to the

chip, and 33Ω terminating resistors can be used on clock outputs with traces longer than 1 inch.

Electrical Specifications

Parameter

Conditions

ABSOLUTE MAXIMUM RATINGS (Note 1)

Supply Voltage, VDD

Referenced to GND

Inputs and Clock Outputs

Ambient Operating Temperature

Soldering Temperature

Max of 10 seconds

Storage Temperature

DC CHARACTERISTICS (VDD = 5V unless noted)

Operating Voltage, VDD

Input High Voltage, VIH

Input Low Voltage, VIL

Output High Voltage

IOH=-4mA

Output High Voltage

IOH=-25mA

Output Low Voltage

IOL=25mA

Operating Supply Current, IDD

No Load, VDD=5.0V

Short Circuit Current

Each output

Input Capacitance

Actual mean frequency error versus target, note 2 Any clock selection

AC CHARACTERISTICS (VDD = 5V unless noted)

Input Frequency, NTSC

Input Frequency, PAL

Output Clock Rise Time

0.8 to 2.0V

Output Clock Fall Time

2.0 to 0.8V

Output Clock Duty Cycle, High Time

At VDD/2

Absolute Clock Period Jitter

Output Enable Time, OE high to outputs on

Output Disable Time, OE low to tri-state

Minimum

-0.5

0

-65

4.5

2

VDD-0.4

2.4

40

Typical Maximum

7

VDD+0.5

70

250

150

5.5

0.8

0.4

15

±100

7

0

1

15.734264

15.625

1.5

1.5

49 to 51

60

TBD

50

3

Units

V

V

°C

°C

°C

V

V

V

V

V

V

mA

mA

pF

ppm

kHz

kHz

ns

ns

%

ps

ns

µs

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure

to levels above the operating limits but below the Absolute Maximums may affect device reliability.

2. Most selections have zero ppm error. Some selections have a maximum of 1 ppm synthesis error .

MDS 1573-02 B

3

Revision 120497

Printed 11/15/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•www.icst.com

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