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MCM69Q536TQ10 Datasheet PDF : 12 Pages
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MCM69Q536/D
Advance Information
32K x 36 Bit Synchronous
Separate I/O SRAM
MCM69Q536
The Motorola MCM69Q536 is a 1 Megabit static random access memory, organized
as 32K words of 36 bits. It features separate data input and data output buffers and
incorporates input and output registers on board with high speed SRAM.
The MCM69Q536 allows the user to perform transparent writes and data pass
through. Two data bus ports are provided — a data input (D) and a data output (Q) port.
The synchronous design allows for precise cycle control with the use of an external
single clock (K). Address port, data input (D0 – D35), data output (Q0 – Q35), write en-
able (W), chip enables (E1, E2), and pass–through enable (PT) are registered on the
rising edge of clock (K).
Any given cycle operates on only one address. However, for any cycle, reads and
writes can be intermixed. Thus, one can perform a read, a write, or a combination read/
write during any one cycle. For a combination read/write, the contents of the array are
read before the new data is written.
By using the pass–through function, the output port Q can be made to reflect either
the contents of the array or the data presented to the input port D. For read/write or a
read cycle with G low, the Q port will output the contents of the array. However, if PT
is asserted, the Q port will instead output the data presented at the D input port.
• Single 3.3 V ± 5% Power Supply
• Fast Access Times: 6/8/10 ns Max
• Sustained Throughput of 2.98 Gigabits/Second
• Single Clock Operation
• Address, Data Input, E1, E2, PT, W, and Data Output Registers on Chip
• 83 MHz Maximum Clock Cycle Time
• Self Timed Write
• Separate Data Input and Data Output Pins
• Pass–Through Feature
• Asynchronous Output Enable (G)
• LVTTL Compatible I/O
• No Dead Cycles Required for Reads after Writes or for Writes after Reads
• 176 Pin TQFP Package
• Simultaneous Reads and Writes
Suggested Applications
— ATM
— Ethernet Switches — Routers
— Cell/Frame Buffers — SNA Switches
— Shared Memory
Product Family Configurations
Part
Number
MCM69D536
MCM69D618
MCM69Q536
MCM69Q618
MCM67Q709
MCM67Q909
Dual
Single
Dual
Separate
Address Address
I/O
n
Note 1
n
n
Note 1
n
n
n
n
n
I/O
Note 2
Note 2
n
n
n
n
NOTES:
1. Tie AX and AY address ports together for the part to function as a single address part.
2. Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
TQ PACKAGE
176 LEAD TQFP
CASE 1101–01
REV 3
11/20/97
M© OMoTtoOroRla,OInLc.A19F97AST SRAM
MCM69Q536
1
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