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MC10H131 Datasheet PDF : 4 Pages
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MC10H131
MAXIMUM RATINGS
Symbol
Characteristic
Rating
Unit
VEE
VI
Iout
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current – Continuous
– Surge
–8.0 to 0
Vdc
0 to VEE
Vdc
50
mA
100
TA
Operating Temperature Range
Tstg
Storage Temperature Range – Plastic
– Ceramic
0 to +75
°C
–55 to +150
°C
–55 to +165
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)
0°
25°
75°
Symbol
Characteristic
Min
Max
Min
Max
Min
Max
Unit
IE
Power Supply Current
IinH
Input Current High
Pins 6, 11
Pin 9
Pins 7, 10
Pins 4, 5, 12, 13
IinL
Input Current Low
VOH
High Output Voltage
VOL
Low Output Voltage
VIH
High Input Voltage
VIL
Low Input Voltage
AC PARAMETERS
–
62
–
56
–
–
530
–
310
–
–
660
–
390
–
–
485
–
285
–
–
790
–
465
–
62
mA
µA
310
390
285
465
0.5
–
0.5
–
0.3
–
µA
–1.02 –0.84 –0.98 –0.81 –0.92
–0.735
Vdc
–1.95 –1.63 –1.95 –1.63 –1.95
–1.60
Vdc
–1.17 –0.84 –1.13 –0.81 –1.07
–0.735
Vdc
–1.95 –1.48 –1.95 –1.48 –1.95
–1.45
Vdc
tpd
Propagation Delay
Clock, CE
Set, Reset
ns
0.8
1.6
0.8
1.7
0.8
1.8
0.6
1.6
0.7
1.7
0.7
1.8
tr
Rise Time
0.6
2.0
0.6
2.0
0.6
2.2
ns
tf
Fall Time
0.6
2.0
0.6
2.0
0.6
2.2
ns
tset
Set–up Time
0.7
–
0.7
–
0.7
–
ns
thold
Hold Time
0.8
–
0.8
–
0.8
–
ns
ftog
Toggle Frequency
250
–
250
–
250
–
MHz
1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm is
maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.
APPLICATION INFORMATION
The MC10H131 is a dual master–slave type D flip–flop.
Asynchronous Set (S) and Reset (R) override Clock (CC)
and Clock Enable (CE) inputs. Each flip–flop may be
clocked separately by holding the common clock in the new
low state and using the enable inputs for the clocking
function. If the common clock is to be used to clock the
flip–flop, the Clock Enable inputs must be in the low state.
In this case, the enable inputs perform the function of
controlling the common clock.
The output states of the flip–flop change on the positive
transition of the clock. A change in the information present
at the data (D) input will not affect the output information at
any other time due to master slave construction.
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