27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
PCLK_OUT
0.8V
PCLK_OUT SHOWN FOR R/F = HIGH (RISING LATCH EDGE)
DE_OUT
LOCK
RGB_OUT[17:0]
CNTL_OUT[8:0]
tDVB
2.0V
0.8V
Figure 5. Synchronous Output Timing
2.0V
tDVA
2.0V
0.8V
IN+, IN-
20 SERIAL BITS
SERIAL-WORD N
PCLK_OUT
CNTL_OUT
RGB_OUT
Figure 6. Deserializer Delay
PCLK_OUT SHOWN FOR R/F = HIGH
SERIAL-WORD N + 1
tDELAY
PARALLEL-WORD N - 1
PARALLEL-WORD N
8 _______________________________________________________________________________________