MAX8833(2007) Ver la hoja de datos (PDF) - Maxim Integrated

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Fabricante

MAX8833
(Rev.:2007)

Dual, 3A, 2MHz Step-Down Regulator

Maxim Integrated 

Dual, 3A, 2MHz Step-Down Regulator

The power-good, open-drain output for regulator 2

(PWRGD2) is high impedance when VSS2 ≥ 0.54V and

VFB2 ≥ 0.9 x VSS2. PWRGD2 is low when VSS2 < 0.54V,

EN2 is low, VVDD or VIN2 is below VUVLO, the thermal-over-

load protection is activated, or when VFB2 < 0.9 x VSS2.

External Reference Input (REFIN)

The MAX8833 has an external reference input. Connect

an external reference between 0 and VVDD - 1.6V to

REFIN to set the FB1 regulation voltage. To use the inter-

nal 0.6V reference, connect REFIN to SS1. When the IC

is shut down, REFIN is pulled to GND through 335Ω.

Startup and Sequencing

The MAX8833 features separate enable inputs (EN1

and EN2) for the two regulators. Driving EN_ high

enables the corresponding regulator; driving EN_ low

turns the regulator off. Driving both EN1 and EN2 low

puts the IC in low-power shutdown mode, reducing the

supply current typically to 30nA. The MAX8833 regula-

tors power up when the following conditions are met

(see Figure 2):

• EN_ is logic-high.

• VVDD is above the UVLO threshold.

• VIN_ is above the UVLO threshold.

• The internal reference is powered.

• The IC is not in thermal overload (TJ < +165°C).

Once these conditions are met, the MAX8833 begins

soft-start. FB2 regulates to the voltage at SS2. During

soft-start, the SS2 capacitor is charged with a constant

8µA current source so that its voltage ramps up for the

RRUVB

THERM

IN1

SHDN

TLIM

UVLO

UVLO

BIAS

GEN

EN1

REF

EN2

RRUVB

UVLO

UVLO

TLIM

IN2

THERM

SHDN

REG1 ON

VDD

REF

RDY

RRUVB

UVLO

REG2 ON

Figure 2. Startup Control Diagram

soft-start time. See the Setting the Soft-Start Time sec-

tion to select the SS2 capacitor for the desired soft-start

time. FB1 regulates to the voltage at REFIN. Connect

REFIN to SS1 to use the internal reference with soft-

start time set independently by the SS1 capacitor (see

Figure 3a).

EN1

OUT1

PWRGD1

EN2

OUT2

PWRGD2

10kΩ

10kΩ

PWRGD1 EN1

EN1

VDD

EN2

EN2

PWRGD2 SS2

SS1

REFIN

Figure 3a. Startup and Sequencing Options—Two Independent Output Startup and Shutdown Waveforms

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