MAX8649(2009) Ver la hoja de datos (PDF) - Maxim Integrated

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MAX8649
(Rev.:2009)

1.8A Step-Down Regulator with Remote Sense in 2mm x 2mm WLP

Maxim Integrated 

1.8A Step-Down Regulator with Differential

Remote Sense in 2mm x 2mm WLP

PIN

A1

A2

A3

A4

B1

B2

B3, B4

C1

C2

C3, C4

D1

D2

D3

D4

NAME

IN1

AGND

VID1

IN2

SNS+

EN

LX

SNS-

VID0

PGND

VDD

SDA

SCL

SYNC

Pin Description

FUNCTION

Analog Supply Voltage Input. The input voltage range is 2.5V to 5.5V. Place an 11Ω resistor between

IN1 and the input supply. Bypass the input supply with a 2.2µF ceramic capacitor as close as

possible to the 11Ω resistor. Bypass IN1 to the 2.2µF capacitor ground plane terminal with a 0.1µF

ceramic capacitor as close as possible to the IC. Connect IN1 and IN2 to the same power source.

Analog Ground. Connect AGND to the PCB ground plane.

Voltage ID Control Input. The logic states of VID0 and VID1 select the register that sets the output

voltage.

Power-Supply Voltage Input. The input voltage range is from 2.5V to 5.5V. IN2 powers the internal

p-channel and n-channel MOSFETs. Bypass IN2 to PGND with 10µF and 0.1µF ceramic capacitors

as close as possible to the IC. Connect IN1 and IN2 to the same power source.

Output Voltage Remote Sense, Positive Input. Connect SNS+ directly to the output at the load.

Logic Enable Input. Drive EN high to enable the DC-DC step-down regulator, or low to place in

shutdown mode. In shutdown mode, this logic input has an internal pulldown resistor to AGND.

Inductor Connection. LX is connected to the drains of the internal p-channel and n-channel

MOSFETs. LX is high impedance during shutdown.

Output Voltage Remote Sense, Negative Input. Connect to a quiet ground directly at the load.

Voltage ID Control Input. The logic states of VID0 and VID1 select the register that sets the output

voltage.

Power Ground. Connect both PGND bumps to the PCB ground plane.

Logic Input Supply Voltage. Connect VDD to the logic supply driving SDA, SCL, and SYNC. Bypass

VDD to AGND with a 0.1µF ceramic capacitor. When VDD drops below the UVLO threshold, the I2C

registers are reset, but the EN control is still active in this mode.

I2C Data Input. Data is read on the rising edge of SCL and data is clocked out on the falling edge of SCL.

I2C Clock Input

External Clock Synchronization Input. Connect SYNC to a 13MHz, 19.2MHz, or 26MHz system clock.

The DC-DC regulator can be forced to synchronize to this external clock depending on I2C setting. See

Table 8. SYNC does not have an internal pulldown. Connect SYNC to AGND if not used.

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