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MAX7472UTI

HDTV Anti-Aliasing Filters with Triple-Input Mux

Minilogic Device Corporation Limited 

HDTV Anti-Aliasing Filters with Triple-Input Mux

As shown in the Sync Detector and Clamp Levels sec-

tion, the low clamp level is used for signals with sync

information and determines the voltage level of the

sync tip, while the high clamp level is used for signals

without sync information and sets the blanking level.

The absolute voltage level of the output signal is rela-

tive to the output clamp level. A video signal containing

sync information (i.e., CVBS or Y) is unipolar above the

clamp level and conversely, a video signal without sync

(i.e., PB, PR, or C) is bipolar around the clamp level.

Multiplexers

The MAX7472/MAX7473 provide four 3:1 multiplexers

programmable through the I2C interface to select which

of three separate channels (channels A, B, C) is to be

connected to each video input. The fourth multiplexer is

used in conjunction with external sync detection and

determines which channel’s external sync is to be con-

nected to the external sync input.

See Table 3 and the Serial Interface section for more

information on how to select a particular channel. After

selecting a channel with a command byte, bits CS7

and CS6 of the Channel Selection register reflect the

channel setting (Table 7).

Power-Down Mode

The MAX7472/MAX7473 include a power-down mode

that reduces the supply current from 180mA (typ) to

1mA (typ) by powering down the analog circuitry. The

I2C interface remains active allowing the device to

return to full-power operation. The clamp settling time

(see the Electrical Characteristics table) limits the

wake-up time of the MAX7472/MAX7473. After exiting

the power-down mode, the MAX7472/MAX7473 resume

normal operation using the settings stored prior to

power-down. The command byte controls the power-

down and wake-up modes (see Table 3). A software

reset sets the Control/Status register to its default con-

ditions. The Frequency register and the Channel

Selection register are not affected.

Power-On Reset (POR)

The MAX7472/MAX7473 include a power-on reset

(POR) circuit that resets the internal registers and I2C

interface to their default condition (see Tables 4–7).

Serial Interface

The MAX7472/MAX7473 feature an I2C-compatible,

2-wire serial interface consisting of a bidirectional serial

data line (SDA) and a serial clock line (SCL). SDA and

SCL facilitate bidirectional communication between the

MAX7472/MAX7473 and the master at rates up to 400kHz.

Once a command byte is written to the MAX7472/

MAX7473, the command interpreter changes the

Control/Status register and the Channel Selection regis-

ter accordingly. See the Control/Status Register and

Channel-Selection Register sections for more informa-

tion. The command interpreter also controls access to

the Frequency register (see the Command Byte (Write

Cycle) section).

The MAX7472/MAX7473 are transmit/receive slave-only

devices, relying upon a master to generate a clock sig-

nal. The master (typically a microcontroller) initiates

data transfer on the bus and generates SCL.

A master device communicates to the MAX7472/

MAX7473 by transmitting the proper address (see the

Slave Address section) followed by a command and/or

data words. Each transmit sequence is framed with a

START (S) or REPEATED START (Sr) condition and a

STOP (P) condition.

The SDA driver is an open-drain output, requiring a

pullup resistor (2.4kΩ or greater) to generate a logic-

high voltage. Optional resistors (24Ω) in series with

SDA and SCL protect the device inputs from high-volt-

age spikes on the bus lines. Series resistors also mini-

mize crosstalk and undershoot of the bus signals.

Bit Transfer

Each SCL rising edge transfers 1 data bit. Nine clock

cycles are required to transfer the data into or out of the

MAX7472/MAX7473. The data on SDA must remain stable

during the high period of the SCL clock pulse. Changes in

SDA while SCL is high are read as control signals (see the

START and STOP Conditions section). When the serial

interface is inactive, SDA and SCL idle high.

START and STOP Conditions

A master device initiates communication by issuing a

START condition (S), a high-to-low transition on SDA with

SCL high (Figure 2). The master terminates transmission

by a STOP condition (P) (see the Acknowledge Bit (ACK)

and Not-Acknowledge Bit (NACK) section). A STOP con-

dition is a low-to-high transition on SDA while SCL is high

(Figure 2). The STOP condition frees the bus. If a repeat-

ed START condition (Sr) is generated instead of a STOP

condition, the bus remains active. When a STOP condi-

tion or incorrect address is detected, the MAX7472/

MAX7473 then ignore all communication on the I2C bus

until the next START or REPEATED START condition,

minimizing digital noise and feedthrough.

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