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MAX7473

HDTV Anti-Aliasing Filters with Triple-Input Mux

Minilogic Device Corporation Limited 

HDTV Anti-Aliasing Filters with Triple-Input Mux

Pin Description (continued)

PIN

NAME

FUNCTION

19

OUT2 Video Output 2. OUT2 can be either AC- or DC-coupled.

21

OUT1 Video Output 1. OUT1 can be either AC- or DC-coupled.

23

A0

Address Bit 0

24

A1

Address Bit 1

27

INA1

Channel A Input 1. AC-couple INA1 with a series 0.1µF capacitor.

28

INB1

Channel B Input 1. AC-couple INB1 with a series 0.1µF capacitor.

Exposed Pad. The exposed pad is located on the package bottom and is internally connected to

—

EP

AGND. Connect EP to the analog ground plane. Do not route any PC board traces under the

package. See the Power-Supply Bypassing and Layout Considerations section.

Detailed Description

The MAX7472/MAX7473 are complete video anti-alias-

ing solutions ideal for fixed-pixel HDTV display tech-

nologies such as plasma and LCD, which digitize the

input video signal and then scale the resolution to

match the native pixel format of the display. With a soft-

ware-selectable corner frequency ranging from 5MHz

to 34MHz, the MAX7472/MAX7473 support both SD

and HD video signals including 1080i, 720p, 720i,

480p, and 480i. Higher bandwidth computer resolution

signals are also supported.

Integrated lowpass filters limit the analog video input

bandwidth for anti-aliasing and out-of-band noise

reduction prior to sampling by an ADC or video

decoder. By allowing the corner frequency to be adjust-

ed from below SD resolution to beyond HD resolutions

in 256 steps, the filter’s corner frequency can be opti-

mized dynamically for a specific input video signal and

the sampling frequency of the ADC or video decoder.

The MAX7472/MAX7473 provide a filter-bypass mode

to support applications requiring a passband greater

than 34MHz.

An I2C interface allows a microcontroller to configure

the MAX7472/MAX7473s’ performance and functionality

including the mux, the clamp voltage, the filter’s corner

frequency, the sync source (internal/external), and filter

bypassing.

The Typical Operating Circuit shows the block diagram

and typical external connections of the MAX7472/

MAX7473.

Sync Detector and Clamp Levels

The MAX7472/MAX7473 use a video clamp circuit to

establish a DC offset for the incoming video signal after

the AC-coupling capacitor. This video clamp sets the DC

bias level of the circuit at the optimum operating point.

The MAX7472/MAX7473 support both internal and

external sync detection. Selection of internal vs. exter-

nal detection is achieved by programming the com-

mand byte (see Table 3). After extracting the sync

information from channel 1 or an external sync (SYNCA,

SYNCB, or SYNCC), the MAX7472/MAX7473 clamp the

video signal during the sync tip portion of the video.

Select one of two possible clamp levels according to

the input signal format. Use the low level when the input

signal contains sync information such as Y (luma) or

CVBS signals. Use the high level for bipolar signals

such as C (chroma) or PB/PR. See Table 1.

Table 1. Clamp Levels

INPUT SIGNAL FORMAT

Y PB PR

GsBR

CVBS Y C

Y PB PR (sync on all signals)

RGBHV

CHANNEL 1

Low

Low

Low

Low

High

CLAMP LEVEL

CHANNEL 2

High

High

Low

Low

High

CHANNEL 3

High

High

High

Low

High

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