MAX7472UTI Ver la hoja de datos (PDF) - Minilogic Device Corporation Limited
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MAX7472UTI Datasheet PDF : 19 Pages
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HDTV Anti-Aliasing Filters with Triple-Input Mux
TIMING CHARACTERISTICS
(AVDD = +5V ±5%, DVDD = 2.7V to 3.6V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Figure 1)
PARAMETER
Serial Clock Frequency
Bus Free Time Between STOP (P)
and START (S) Conditions
SYMBOL
fSCL
tBUF
CONDITIONS
MIN TYP MAX UNITS
0
400
kHz
1.3
µs
Hold Time (Repeated) START (Sr)
Condition
tHD;STA
After this period, the first clock pulse is
generated
0.6
SCL Pulse-Width Low
tLOW
1.3
SCL Pulse-Width High
tHIGH
0.6
Setup Time for a Repeated START
(Sr) Condition
tSU;STA
0.6
Data Hold Time
tHD;DAT (Note 5)
0
Data Setup Time
tSU;DAT
100
Rise Time of Both SDA and SCL
Signals, Receiving
tr
0
µs
µs
µs
µs
0.9
µs
ns
300
ns
Fall Time of Both SDA and SCL
Signals, Receiving
tf
0
300
ns
Fall Time of SDA Signal,
Transmitting
Setup Time for STOP (P) Condition
Capacitive Load for Each Bus Line
Pulse Width of Spikes Suppressed
by the Input Filter
tf
tSU;STO
Cb
tSP
(Note 6)
(Note 7)
20 +
0.1Cb
0.6
0
300
ns
µs
400
pF
50
ns
Note 1: The filter passband edge is set to code 255.
Note 2: The filter passband edge is set to code 40.
Note 3: 1H is the total line period, depending on the video standard. For NTSC, this is 63.5µs, for HDTV, the line period is 29.64µs.
Note 4: The clamp level is at the sync tip for signals with sync pulses, and is at the blanking level otherwise.
Note 5: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 6: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3VDD and 0.7VDD.
Note 7: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
SDA
tf
SCL
tLOW
tSU;DAT
tr
tf
tHD;STA tHD;DAT
S
tHIGH
Figure 1. 2-Wire Serial-Interface Timing Diagram
tSU;STA
Sr
tHD;STA
tBUF
tSP
tr
tSU;STO
P
S
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