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MAX7310

2-Wire-Interfaced 8-Bit I/O Port Expander with Reset

Maxim Integrated 

2-Wire-Interfaced 8-Bit I/O Port Expander

with Reset

Table 1 is the register address table. Tables 2–6 list

register 0 through register 4 information.

Serial Interface

Serial Addressing

The MAX7310 operates as a slave that sends and

receives data through a 2-wire interface. The interface

uses a serial data line (SDA) and a serial clock line

(SCL) to achieve bidirectional communication between

master(s) and slave(s). A master, typically a microcon-

troller, initiates all data transfers to and from the

MAX7310, and generates the SCL clock that synchro-

nizes the data transfer (Figure 2).

Each transmission consists of a start condition sent by

a master, followed by the MAX7310 7-bit slave address

plus an R/W bit, a register address byte, one or more

data bytes, and finally a stop condition (Figure 3).

Start and Stop Conditions

Both SCL and SDA remain high when the interface is

not busy. A master signals the beginning of a transmis-

sion with a start (S) condition by transitioning SDA from

high to low while SCL is high. When the master has fin-

ished communicating with the slave, it issues a stop (P)

condition by transitioning SDA from low to high while

SCL is high. The bus is then free for another transmis-

sion (Figure 3).

Bit Transfer

One data bit is transferred during each clock pulse.

The data on SDA must remain stable while SCL is high

(Figure 4).

Acknowledge

The acknowledge bit is a clocked 9th bit, which the

recipient uses as a handshake receipt of each byte of

data (Figure 5). Thus, each byte transferred effectively

requires 9 bits. The master generates the 9th clock

pulse, and the recipient pulls down SDA during the

acknowledge clock pulse, such that the SDA line is sta-

ble low during the high period of the clock pulse. When

the master is transmitting to the MAX7310, the

MAX7310 generates the acknowledge bit since the

MAX7310 is the recipient. When the MAX7310 is trans-

mitting to the master, the master generates the

acknowledge bit.

Slave Address

The MAX7310 has a 7-bit-long slave address (Figure

6). The 8th bit following the 7-bit slave address is the

R/W bit. Set this bit low for a write command and high

for a read command.

SDA

tSU, DAT

tLOW

SCL

tHD, DAT

tHD, STA

tHIGH

tR

tF

START CONDITION

Figure 2. 2-Wire Serial Interface Timing Diagrams

SDA

tSU, STA

tHD, STA

REPEATED START CONDITION

tBUF

tSU, STO

STOP CONDITION START CONDITION

SCL

S

START

CONDITION

P

STOP

CONDITION

Figure 3. Start and Stop Conditions

6 _______________________________________________________________________________________

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