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MAX7319

I2C Port Expander with Eight Inputs and Maskable Transition Detection

Maxim Integrated 

MAX7319

I2C Port Expander with Eight Inputs

and Maskable Transition Detection

SDA

tLOW

tSU,DAT

tHD,DAT

tSU,STA

tHD,STA

tBUF

tSU,STO

SCL

tHIGH

tHD,STA

tR

tF

START CONDITION

REPEATED START CONDITION

STOP

START

CONDITION CONDITION

Figure 1. 2-Wire Serial-Interface Timing Details

SDA operates as both an input and an open-drain

output. A pullup resistor, typically 4.7kΩ, is required on

SDA. SCL operates only as an input. A pullup resistor,

typically 4.7kΩ, is required on SCL if there are multiple

masters on the 2-wire interface, or if the master in a

single-master system has an open-drain SCL output.

Each transmission consists of a START condition sent

by a master, followed by the MAX7319’s 7-bit slave

address plus R/W bit, then 1 or more data bytes, and

finally a STOP condition (Figure 2).

Start and Stop Conditions

Both SCL and SDA remain high when the

interface is not busy. A master signals the beginning of a

transmission with a START (S) condition by transitioning

SDA from high to low while SCL is high. When the master

has finished communicating with the slave, the master

issues a STOP (P) condition by transitioning SDA from

low to high while SCL is high. The bus is then free for

another transmission (Figure 2).

Bit Transfer

One data bit is transferred during each clock pulse.

The data on SDA must remain stable while SCL is high

(Figure 3).

Acknowledge

The acknowledge bit is a clocked 9th bit the recipient

uses to acknowledge receipt of each byte of data

(Figure 4). Each byte transferred effectively requires 9

bits. The master generates the 9th clock pulse, and

the recipient pulls down SDA during the acknowledge

clock pulse, so the SDA line is stable low during the

high period of the clock pulse. When the master is

transmitting to the MAX7319, the MAX7319 generates the

acknowledge bit because the device is the recipient.

SDA

SCL S

START

CONDITION

Figure 2. Start and Stop Conditions

P

STOP

CONDITION

SDA

SCL

DATA LINE STABLE; CHANGE OF DATA

DATA VALID

ALLOWED

Figure 3. Bit Transfer

START

CONDITION

SCL

1

SDA BY

TRANSMITTER

SDA BY

RECEIVER S

Figure 4. Acknowledge

CLOCK PULSE

FOR ACKNOWLEDGMENT

2

8

9

When the MAX7319 is transmitting to the master, the

master generates the acknowledge bit because the

master is the recipient.

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