MAX7311 Ver la hoja de datos (PDF) - Maxim Integrated
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MAX7311
Maxim Integrated
MAX7311 Datasheet PDF : 16 Pages
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2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
Data is clocked into a register on the falling edge of the
acknowledge clock pulse. After reading the first byte,
additional bytes may be read and reflect the content in
the other register in the pair. For example, if input port 1
is read, the next byte read is input port 2. An unlimited
number of data bytes can be read in one read trans-
mission, but the final byte received must not be
acknowledged by the bus master.
Interrupt (INT)
The open-drain interrupt output, INT, activates when
one of the port pins changes states and only when the
pin is configured as an input. The interrupt deactivates
when the input returns to its previous state or the input
register is read (Figure 9). A pin configured as an out-
put does not cause an interrupt. Each 8-bit port register
is read independently; therefore, an interrupt caused
by port 1 is not cleared by a read of port 2’s register.
Changing an I/O from an output to an input may cause
a false interrupt to occur if the state of that I/O does not
match the content of the input port register.
Input/Output Port
When an I/O is configured as an input, FETs Q1 and Q2
are off (Figure 10), creating a high-impedance input with
a nominal 100kΩ pullup to V+. All inputs are overvoltage
protected to 5.5V, independent of supply voltage. When
a port is configured as an output, either Q1 or Q2 is on,
depending on the state of the output port register. When
V+ powers up, an internal power-on reset sets all regis-
ters to their respective defaults (Table 1).
Input Port Registers
The input port registers (Table 2) are read-only ports.
They reflect the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or
an output by the respective configuration register. A
read of the input port 1 register latches the current
value of I/O0–I/O7. A read of the input port 2 register
latches the current value of I/O8–I/O15. Writes to the
input port registers are ignored.
CONFIGURATION
REGISTER
DATA FROM
SHIFT REGISTER
SET
DQ
Q1
WRITE
CONFIGURATION
PULSE
DATA FROM
SHIFT REGISTER
WRITE PULSE
READ PULSE
POWER-ON
RESET
DATA FROM
SHIFT REGISTER
WRITE POLARITY
PULSE
Q
CLR
SET
DQ
Q
CLR
OUTPUT PORT
REGISTER
INPUT PORT
REGISTER
SET
DQ
Q
CLR
SET
DQ
Q
CLR
POLARITY INVERSION
REGISTER
Figure 10. Simplified Schematic of I/Os
100kΩ
OUTPUT PORT
REGISTER DATA
VDD
I/O PIN
Q2
VSS
INPUT PORT
REGISTER DATA
TO INT
POLARITY
REGISTER
DATA
10 ______________________________________________________________________________________
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