MAX7312 Ver la hoja de datos (PDF) - Maxim Integrated
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componentes Descripción
Fabricante
MAX7312
Maxim Integrated
MAX7312 Datasheet PDF : 16 Pages
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2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
DC ELECTRICAL CHARACTERISTICS (continued)
(V+ = 2V to 5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.) (Note 1)
PARAMETER
Leakage Current
Input Capacitance
INT
Low-Level Output Current
SYMBOL
CONDITIONS
IOL
VOL = 0.4V
MIN TYP MAX
-1
+1
4
6
UNITS
µA
pF
mA
AC ELECTRICAL CHARACTERISTICS
(V+ = 2V to 5.5V, TA = -40°C to +125°C, unless otherwise noted.) (Note 1)
PARAMETER
SCL Clock Frequency
Bus Timeout
Bus Free Time Between STOP
and START Conditions
SYMBOL
fSCL
tTIMEOUT
(Note 2)
tBUF Figure 2
CONDITIONS
MIN TYP MAX UNITS
400
kHz
29
61
ms
1.3
µs
Hold Time (Repeated) START
Condition
tHD,STA Figure 2
0.6
µs
Repeated START Condition
Setup Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Low Period
SCL High Period
SDA Fall Time
Pulse Width of Spike Suppressed
PORT TIMING
Output Data Valid
Input Data Setup Time
Input Data Hold Time
INTERRUPT TIMING
Interrupt Valid
Interrupt Reset
tSU,STA Figure 2
tSU,STO
tHD,DAT
tSU,DAT
tLOW
tHIGH
Figure 2
Figure 2 (Note 3)
Figure 2
Figure 2
Figure 2
tF
Figure 2 (Notes 4, 5)
tSP
(Note 6)
tPV
Figure 7
tIV
Figure 9
tIR
Figure 9
V+ < 3.3V
V+ ≥ 3.3V
0.6
µs
0.6
µs
0.9
µs
100
ns
1.3
µs
0.7
µs
500
ns
250
50
ns
3
µs
27
µs
0
µs
30.5
µs
2
µs
Note 1: All parameters are 100% production tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Minimum SCL clock frequency is limited by the MAX7312 bus timeout feature, which resets the serial bus interface if either
SDA or SCL is held low for a minimum of 25ms. Disable bus timeout feature for DC operation.
Note 3: A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIL of the SCL
signal) in order to bridge the undefined region SCL’s falling edge.
Note 4: CB = total capacitance of one bus line in pF.
Note 5: The maximum tF for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage tF is
specified at 250ns. This allows series protection resistors to be connected between the SDA and SCL pins and the
SDA/SCL bus lines without exceeding the maximum specified tF.
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
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