MAX7300AAX Ver la hoja de datos (PDF) - Maxim Integrated

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MAX7300AAX

2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander

Maxim Integrated 

2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or

28-Port I/O Expander

COMMAND BYTE IS STORED ON RECEIPT OF STOP CONDITION

ACKNOWLEDGE FROM MAX7300

D15 D14 D13 D12 D11 D10 D9 D8

S

SLAVE ADDRESS

0A

COMMAND BYTE

AP

Figure 7. Command Byte Received

R/W

ACKNOWLEDGE FROM MAX7300

HOW COMMAND BYTE AND DATA BYTE MAP INTO MAX7300’s REGISTER

ACKNOWLEDGE FROM MAX7300

ACKNOWLEDGE FROM MAX7300

D15 D14 D13 D12 D11 D10 D9 D8

ACKNOWLEDGE FROM MAX7300

D7 D6 D5 D4 D3 D2 D1 D0

S

SLAVE ADDRESS

0A

COMMAND BYTE

A

DATA BYTE

AP

R/W

1 BYTE

AUTOINCREMENT MEMORY WORD ADDRESS

Figure 8. Command and Single Data Byte Received

tions on that port are to be ignored. Transition detection

works regardless of whether the port being monitored is

set to input or output, but generally, it is not particularly

useful to enable transition detection for outputs.

To use transition detection, first set up the mask regis-

ter and configure port P31 as an output, as described

above. Then enable transition detection by setting the

M bit in the configuration register (Table 9). Whenever

the configuration register is written with the M bit set,

the MAX7300 updates an internal 7-bit snapshot regis-

ter, which holds the comparison copy of the logic states

of ports P24 through P30. The update action occurs

regardless of the previous state of the M bit, so that it is

not necessary to clear the M bit and then set it again to

update the snapshot register.

When the configuration register is written with the M bit

set, transition detection is enabled and remains

enabled until either the configuration register is written

with the M bit clear, or a transition is detected. The INT

status bit (transition detection mask register bit D7)

goes low. Port P31 (if enabled as INT output) also goes

low, if it was not already low.

Once transition detection is enabled, the MAX7300

continuously compares the snapshot register against

the changing states of P24 through P31. If a change on

any of the monitored ports is detected, even for a short

time (like a pulse), the INT status bit (transition detec-

tion mask register bit D7) is set. Port P31 (if enabled as

INT output) also goes high. The INT output and INT sta-

tus bit are not cleared if more changes occur or if the

data pattern returns to its original snapshot condition.

The only way to clear INT is to access (read or write)

the transition detection mask register (Table 10). So if

the transition detection mask register is read twice in

succession after a transition event, the first time reads

with bit D7 set (identifying the event), and the second

time reads with bit D7 clear.

Transition detection is a one-shot event. When INT has

been cleared after responding to a transition event, tran-

sition detection is automatically disabled, even though

the M bit in the configuration register remains set (unless

cleared by the user). Reenable transition detection by

writing the configuration register with the M bit set to

take a new snapshot of the seven ports P24 to P30.

External Component RISET

The MAX7300 uses an external resistor, RISET, to set

internal biasing. Use a resistor value of 39kΩ.

Applications Information

Low-Voltage Operation

The MAX7300 operates down to 2V supply voltage

(although the sourcing and sinking currents are not guar-

anteed), providing that the MAX7300 is powered up ini-

tially to at least 2.5V to trigger the device’s internal reset.

Serial Interface Latency

When a MAX7300 register is written through the I2C

interface, the register is updated on the rising edge of

SCL during the data byte’s acknowledge bit (Figure 5).

The delay from the rising edge of SCL to the internal

register being updated can range from 50ns to 350ns.

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