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Fabricante

MAX7034

315MHz/434MHz ASK Superheterodyne Receive

Maxim Integrated 

MAX7034

315MHz/434MHz ASK Superheterodyne

Receiver

It is possible to use an external reference oscillator in

place of a crystal to drive the VCO. AC-couple the exter-

nal oscillator to XTAL2 with a 1000pF capacitor. Drive

XTAL2 with a signal level of approximately 500mVP-P.

AC-couple XTAL1 to ground with a 1000pF capacitor.

Data Filter

The data filter is implemented as a 2nd-order lowpass

Sallen-Key filter. The pole locations are set by the

combination of two on-chip resistors and two external

capacitors. Adjusting the value of the external capacitors

changes the corner frequency to optimize for different

data rates. The corner frequency should be set to approxi-

mately 1.5 times the fastest expected data rate from the

transmitter. Keeping the corner frequency near the data

rate rejects any noise at higher frequencies, resulting in

an increase in receiver sensitivity.

The configuration shown in Figure 1 can create a

Butterworth or Bessel response. The Butterworth filter

offers a very flat amplitude response in the passband and

a rolloff rate of 40dB/decade for the two-pole filter. The

Bessel filter has a linear phase response, which works

well for filtering digital data. To calculate the value of C7

and C6, use the following equations, along with the coef-

ficients in Table 1:

C7

=

b

a(100k)(π)(f

C)

C6

=

a

4(100k)(π)(fC)

where fC is the desired 3dB corner frequency.

For example, to choose a Butterworth filter response with

a corner frequency of 5kHz:

C7

1.000

(1.414)(100kΩ)(3.14)(5kHz)

≈

450pF

= C6

1.414

(4)(100kΩ)(3.14)(5kHz)

≈

225pF

Choosing standard capacitor values changes C7 to 470pF

and C6 to 220pF, as shown in the Typical Application Circuit.

Data Slicer

The data slicer takes the analog output of the data filter and

converts it to a digital signal. This is achieved by using a

comparator and comparing the analog input to a threshold

voltage. One input is supplied by the data filter output. Both

comparator inputs are accessible off-chip to allow for dif-

ferent methods of generating the slicing threshold, which is

applied to the second comparator input.

The suggested data slicer configuration uses a resistor

(R1) connected between DSN and DSP with a capacitor

(C8) from DSN to DGND (Figure 2). This configuration

averages the analog output of the filter and sets the

threshold to approximately 50% of that amplitude. With

this configuration, the threshold automatically adjusts as

the analog signal varies, minimizing the possibility for

errors in the digital data. The values of R1 and C8 affect

how fast the threshold tracks to the analog amplitude. Be

sure to keep the corner frequency of the RC circuit much

lower than the lowest expected data rate.

Note that a long string of zeros or ones can cause the

threshold to drift. This configuration works best if a coding

scheme, such as Manchester coding, which has an equal

number of zeros and ones, is used.

To prevent continuous toggling of DATAOUT in the

absence of an RF signal due to noise, add hysteresis to

the data slicer as shown in Figure 3.

Table 1. Coefficents to Calculate C7 and C6

FILTER TYPE

Butterworth (Q = 0.707)

Bessel (Q = 0.577)

a

1.414

1.3617

b

1.000

0.618

MAX7034

RDF2

100kΩ

RSSI

RDF1

100kΩ

19

21

22

DFO

OPP

DFFB

C6

C7

Figure 1. Sallen-Key Lowpass Data Filter

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