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MAX5138

Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs

Maxim Integrated 

MAX5138/MAX5139

Low-Power, Single, 16-/12-Bit,

Buffered Voltage-Output DACs

AVDD as Reference

Connect AVDD to REFI to use AVDD as the reference

voltage. Leave REFO unconnected.

Serial Interface

The MAX5138/MAX5139 3-wire serial interface is com-

patible with MICROWIRE, SPI, QSPI, and DSPs (Figures

2, 3). The interface provides three inputs, SCLK, CS,

and DIN and one output, READY. Use READY to verify

communication or to daisy-chain multiple devices (see

the READY section). READY is capable of driving a

20pF load with a 30ns (max) delay from the falling edge

of SCLK. The chip-select input (CS) frames the serial

data loading at DIN. Following a chip-select input’s

high-to-low transition, the data is shifted synchronously

and latched into the input register on each falling edge

of the serial-clock input (SCLK). Each serial word is 24

bits. The first 8 bits are the control word followed by 16

data bits (MSB first), as shown in Table 1. The serial

input register transfers its contents to the input registers

after loading 24 bits of data. To initiate a new data

transfer, drive CS high and keep CS high for a minimum

of 33ns before the next write sequence. The SCLK can

be either high or low between CS write pulses. Figure 1

shows the timing diagram for the complete 3-wire serial-

interface transmission.

The MAX5138/MAX5139 digital input is double buffered.

Depending on the command issued through the serial

interface, the input register can be loaded without affect-

ing the DAC register using the write command. To update

the DAC register, either pulse the LDAC input low, or use

the software LDAC command. Use the writethrough com-

mands (see Table 1) to update the DAC output immedi-

ately after the data is received. Only use the writethrough

command to update the DAC output immediately.

Table 1. Operating Mode Truth Table

24-BIT WORD

CONTROL BITS

DATA BITS

MSB

C7 C6 C5 C4 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8

0 000000 0 X X X X X X X X

DESC

LSB

FUNCTION

D7 D6–D0

X

X NOP No operation.

0 0 0 0 0 0 0 1 X X X X X X X DAC

X

0 000001 0 X X X X X X X X

X

Set DAC = 1 to move

X

LDAC

contents of input to DAC

register. Setting DAC = 0

results in no operation.

X

CLR Software clear.

Set DAC = 1 to power

down DAC. Set

0 000001 1 X X X X

X

X X DAC READY_EN X

Power READY_EN = 1 to

Control enable READY. Setting

DAC = 0 results in no

operation.

0 0 0 0 0 1 0 1 0 0 0 0 0 0 LIN 0

0

0 0 0 1 X X X DAC D15 D14 D13 D12 D11 D10 D9 D8

D7

0 Linearity Optimize DAC linearity.

Write to selected input

registers (DAC output

D6 Write not affected). Setting

DAC = 0 results in no

operation.

0 0 1 1 X X X DAC D15 D14 D13 D12 D11 D10 D9 D8

D7

Write to selected input

and DAC register,

Write- DAC output updated

D6 through (writethrough). Setting

DAC = 0 results in no

operation.

0 010000 0 X X X X X X X X

X

X NOP No operation.

*For the MAX5139, D3–D0 are X = don’t-care bits.

10

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