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MAX5057AASA

4A, 20ns, Dual MOSFET Drivers

Maxim Integrated 

4A, 20ns, Dual MOSFET Drivers

Table 1. MAX5054 Truth Table

INA+/INB+

Low

Low

High

High

INA-/INB-

Low

High

Low

High

OUTA/OUTB

Low

Low

High

Low

Table 2. MAX5055/MAX5056/MAX5057

Truth Table

IN_+

Low

High

IN_-

Low

High

NONINVERTING

INVERTING

OUT_

Low

High

OUT_

High

Low

The logic inputs are high impedance and must not be left

floating. If the inputs are left open, OUT_ can go to an

undefined state as soon as VDD rises above the UVLO

threshold. Therefore, the PWM output from the controller

must assume proper state when powering up the device.

The MAX5054 has two logic inputs per driver providing

greater flexibility in controlling the MOSFET. Use IN_+ for

noninverting logic and IN_- for inverting logic operation.

Connect IN_+ to VDD and IN_- to GND if not used.

Alternatively, the unused input can be used as an

ON/OFF function. Use IN_+ for active-low shutdown logic

and IN_- for active-high shutdown logic (see Figure 4).

See Table 1 for all possible input combinations.

Driver Output

The MAX5054–MAX5057 have low RDS(ON) p-channel

and n-channel devices (totem pole) in the output stage

for the fast turn-on and turn-off high gate-charge switch-

ing MOSFETs. The peak source or sink current is typically

4A. The OUT_ voltage is approximately equal to VDD

when in high state and is ground when in low state. The

driver RDS(ON) is lower at higher VDD, thus higher

source-/sink-current capability and faster switching

speeds. The propagation delays from the noninverting

and inverting logic inputs to outputs are matched to 2ns.

The break-before-make logic avoids any cross-conduc-

tion between the internal p- and n-channel devices, and

eliminates shoot-through currents reducing the quiescent

supply current.

PWM

INPUT

ON

VDD

MAX5054A

INA+

OUTA

OFF

INA- GND

Figure 4. Unused Input as an ON/OFF Function (1/2 MAX5054A)

Applications Information

RLC Series Circuit

The driver’s RDS(ON) (RON), internal bond and lead

inductance (LP), trace inductance (LS), gate inductance

(LG), and gate capacitance (CG) form a series RLC

circuit with a second-order characteristic equation. The

series RLC circuit has an undamped natural frequency

(ϖ0) and a damping ratio (ζ) where:

ϖ0 =

1

(LP + LS + LG ) × CG

ξ=

2×

RON

(LP + LS + LG )

CG

The damping ratio needs to be greater than 0.5 (ideally 1)

to avoid ringing. Add a small resistor (RGATE) in series

with the gate when driving a very low gate-charge

MOSFET, or when the driver is placed away from the

MOSFET. Use the following equation to calculate the

series resistor:

RGATE ≥

(LP

+ LS + LG )

CG

− RON

LP can be approximated as 3nH and 2nH for SO and

TDFN packages, respectively. LS is on the order of

20nH/in. Verify LG with the MOSFET vendor.

10 ______________________________________________________________________________________

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