Low-Voltage, 60Ω,
4:1 Analog Multiplexer in QFN
Test Circuits/Timing Diagrams
V+
VADD
V+
ADDA
NO0
VNO_
ADDB
NO1–NO2
MAX4704 NO3
V+
VADD
0
VNO0
INH
COM
GND
300Ω
VOUT
35pF
VOUT
0
50%
90%
tTRANS
90%
tTRANS
Figure 2. Address Transition Time
V+
V+
ADDA
NO0
VNO_
ADDB
NO1–NO3
MAX4704
VINH
INH
COM
GND
300Ω
VOUT
35pF
V+
VINH
50%
0
VNO0
90%
VOUT
0
tOFF
90%
tON
Figure 3. Inhibit Switching Times
V+
VADD
V+
ADDA
NO0–N03
VNO_
ADDB
MAX4704
INH
COM
GND
300Ω
VOUT
35pF
Figure 4. Break-Before-Make Interval
V+
VADD
0
VCOM
VOUT
0
tR < 5ns
50%
tF < 5ns
90%
tBBM
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