0.8Ω, Low-Voltage, Single-Supply Dual SPST
Analog Switches
Test Circuits/Timing Diagrams
V+
OPEN
NO_ V+ NO_
MAX4741
IN_
COM_
50Ω
GND
VNO_
50Ω
VCOM_
35pF
VIH + 0.5V
IN_
0
VNO_
VCOM_
0
tR < 5ns
tF < 5ns
50%
50%
90%
tON
90%
tOFF
V+
OPEN
NC_ V+ NC_
MAX4742
IN_
COM_
50Ω
GND
VNC_
50Ω
VCOM_
35pF
VIH + 0.5V
IN_
0
VNC_
VCOM_
0
50%
50%
90%
tOFF
90%
tON
V+
VS
NC_ V+ NO_
MAX4743
IN_
COM_
50Ω
GND
VS
50Ω
VCOM_
35pF
VIH + 0.5V
IN_
0
VS
VCOM_
0
90%
tBBM
tBBM = tON(NO_) - tOFF(NC_)
OR
tBBM = tON(NC_) - tOFF(NO_)
Figure 1. Switching Times
90%
tBBM
8 _______________________________________________________________________________________