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MAX3942

10Gbps Modulator Driver

Maxim Integrated 

10Gbps Modulator Driver

The input data is retimed on the rising edge of CLK+. If

RTEN is connected to ground, the retiming function is dis-

abled and the input data is directly connected to the out-

put stage. Leave CLK+ and CLK- open when retiming is

disabled.

Pulse-Width Control

The pulse-width control circuit can be used to compen-

sate for pulse-width distortion introduced by the modu-

lator. The differential voltage between PWC+ and PWC-

adjusts the pulse-width compensation. The adjustment

range is typically ±50ps. Optional single-ended opera-

tion is possible by forcing a voltage on the PWC+ pin

while leaving the PWC- pin unconnected. When PWC-

is connected to ground, the pulse-width control circuit

is automatically disabled.

Modulation Output Enable

The MAX3942 incorporates a modulation current-

enable input. When MODEN is low or floating, the mod-

ulation outputs OUT+ and OUT- are enabled. When

MODEN is high, the drive current is switched to OUT+.

The typical enable time is 2ns and the typical disable

time is 2ns.

Design Procedure

Programming the Modulation Voltage

The modulation voltage results from IMOD passing

through the load impedance (ZL) in parallel with the

internal 50Ω termination resistor (ROUT):

VMOD ≈ IMOD

×

ZL × ROUT

ZL + ROUT

To program the desired modulation current, force a

voltage at the MODSET pin (see the Typical Application

Circuit). The resulting IMOD current can be calculated

by the following equation:

IMOD ≈

VMODSET

11.1Ω

+ 37mA

An internal, independent current source drives a constant

37mA to the modulation circuitry and any voltage above

VEE on the MODSET pin adds to this. The input imped-

ance of the MODSET pin is typically 20kΩ. Note that the

minimum output voltage is VEE + 1.9V.

Programming the Pulse-Width Control

Three methods of control are possible when pulse predis-

tortion is desired to minimize distortion at the receiver.

The pulse width may be set with a 2kΩ potentiometer with

the center tapped to VEE (or equivalent fixed resistors), or

by applying a voltage to the PWC+ pin, or by applying a

differential voltage across the PWC+ and PWC- pins. See

Table 1 for the desired effect of the pulse-width setting.

Pulse width is defined as (positive pulse width)/((positive

pulse width + negative pulse width)/2).

Input Termination Requirement

The MAX3942 data and clock inputs are CML compati-

ble. However, it is not necessary to drive the IC with a

standard CML signal. As long as the specified input volt-

age swings are met, the MAX3942 operates properly.

Applications Information

Layout Considerations

To minimize loss and crosstalk, keep the connections

between the MAX3942 output and the modulator as

short as possible. Use good high-frequency layout

techniques and multilayer boards with an uninterrupted

ground plane to minimize EMI and crosstalk. Circuit

boards should be made using low-loss dielectrics. Use

controlled-impedance lines for the clock and data

inputs, as well as for the data output.

Table 1. Pulse-Width Control

PULSE

WIDTH

(%)

RPWC+, RPWC- FOR

RPWC+ + RPWC- = 2kΩ

VPWC+

(PWC- OPEN)

(V)

VPWC+ -

VPWC-

(V)

100

>100

<100

RPWC+ = RPWC-

RPWC+ > RPWC-

RPWC+ < RPWC-

VEE + 1

0

> VEE + 1

>0

< VEE + 1

<0

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