MAX3991UTG Ver la hoja de datos (PDF) - Maxim Integrated

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Fabricante

MAX3991UTG

10Gbps Clock and Data Recovery with Limiting Amplifier

Maxim Integrated 

10Gbps Clock and Data Recovery

with Limiting Amplifier

Pin Description (continued)

PIN

NAME

FUNCTION

Positive Reference Clock Input, Digital. The REFCLK inputs are designed to be AC-coupled to the

21

REFCLK+ reference clock source. REFCLK± have a 200Ω differential impedance. See the Detailed Description

section for more information. See Table 2.

Negative Reference Clock Input, Digital. The REFCLK inputs are designed to be AC-coupled to the

22

REFCLK- reference clock source. REFCLK± have a 200Ω differential impedance. See the Detailed Description

section for more information. See Table 2.

23

FCTL1 Function Control Input 1, TTL. See Table 3 for more information.

LOS Threshold Input, Analog. A voltage applied to this input sets the LOS assert threshold. The LOS

24

VTH

power detector can be disabled if VTH is connected to VCC, which forces LOS low.

EP

Exposed

Pad

Supply Ground. The exposed pad must be soldered to the circuit-board ground for proper thermal

and electrical performance. The MAX3991 uses exposed-pad variation T2444-4 in the package

outline drawing. See the exposed-pad package.

Functional Diagram

VTH LOS

SDI+

CML

SDI-

LIMITING

AMPLIFIER

MAX3991

PLL

PHASE/

FREQUENCY

DETECTOR

DFF

D

Q

CML

VCO

CML

SDO+

SDO-

SCLKO+

SCLKO-

REFCLK+

REFCLK-

200Ω

LOL

DETECTOR

LOL

FUNCTIONAL

CONTROL

FCTL1 FCTL2

CFIL

POL

Figure 3. Functional Diagram

Detailed Description

The MAX3991 clock and data recovery with limiting

amplifier restores data to XFI specifications. It consists of

a limiting amplifier with LOS power detector, and a PLL

data retimer with LOL indicator. An optional recovered

clock may also be enabled for performance testing.

Limiting Amplifier

The SDI inputs of the MAX3991 accept serial NRZ data

from the optical receiver assembly. The limiting amplifier

accepts signals as small as 7mVP-P and amplifies them

to allow recovery by the CDR. The limiting amplifier uses

an offset cancellation circuit to compensate for device

mismatch within the gain stages. The low-frequency cut-

off of the offset cancellation loop is typically 30kHz.

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