MAX3991UTG Ver la hoja de datos (PDF) - Maxim Integrated
Número de pieza
componentes Descripción
Fabricante
MAX3991UTG Datasheet PDF : 12 Pages
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10Gbps Clock and Data Recovery
with Limiting Amplifier
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
SDD22 vs. FREQUENCY
10
5
0
-5
XFI
-10
-15
-20
-25
-30
-35
-40
100M
1G
10G
100G
FREQUENCY (mHz)
SCC22 vs. FREQUENCY
0
-5
XFI
-10
-15
20
-25
-30
-35
100M
1G
10G
100G
FREQUENCY (Hz)
LOS ASSERT/DEASSERT LEVELS
vs. VTH VOLTAGE
160
140 DEASSERT THRESHOLD
120
100
80
60
ASSERT THRESHOLD
40
20
0
0 200 400 600 800 1000 1200 1400 1600
VTH VOLTAGE (mV)
Pin Description
PIN
1, 6, 11, 13, 18
2, 5, 14, 17
3
4
7
8
9
10
12
15
16
19
20
NAME
VCC
GND
SDI+
SDI-
SCLKO+
SCLKO-
FCTL2
POL
CFIL
SDO-
SDO+
LOL
LOS
FUNCTION
+3.3V Power Supply
Supply Ground
Positive Serial Input, CML
Negative Serial Input, CML
Positive Clock Output, CML. See Table 3 for information about enabling the SCLKO output (for use
in device testing).
Negative Clock Output, CML. See Table 3 for information about enabling the SCLKO output (for use
in device testing).
Function Control Input 2, TTL. See Table 3 for more information.
Data Polarity Control Input, TTL. Connect to VCC or leave open to maintain the same polarity as the
input. Connect to GND to invert the polarity of the data.
Loop-Filter Capacitor Connection. Connect a 0.047µF capacitor between CFIL and VCC.
Negative Serial Data Output, CML
Positive Serial Data Output, CML
Lock Status Indicator, TTL. This output goes high to indicate the receiver is out of lock.
Receiver Loss-of-Signal Indicator, TTL . This output goes high when the input signal drops below
the programmed threshold.
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