MAX3885 Ver la hoja de datos (PDF) - Maxim Integrated
Número de pieza
componentes Descripción
Fabricante
MAX3885 Datasheet PDF : 8 Pages
| |||
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
Detailed Description
The MAX3885 deserializer uses a 16-bit shift register,
16-bit parallel output register, 4-bit counter, PECL input
buffers, and low-voltage differential-signal (LVDS)
input/output buffers to convert 2.488Gbps serial data to
16-bit wide, 155Mbps parallel data (Figure 2). The input
SD+
PECL
SD-
SCLK+
SCLK- PECL
SYNC+
SYNC-
100Ω LVDS
16-BIT
SHIFT
REGISTER
16-BIT
PARALLEL
OUTPUT
REGISTER
LVDS
PD15+
PD15-
MAX3885
4-BIT
COUNTER
LVDS
LVDS
LVDS
PD1+
PD1-
PD0+
PD0-
PCLK+
PCLK-
Figure 2. Functional Diagram
shift register continuously clocks incoming data on the
positive transition of the serial clock (SCLK) input sig-
nal. The 4-bit counter generates a parallel-output clock
(PCLK) by dividing the serial-clock frequency by 16.
The PCLK signal clocks the parallel-output register.
During normal operation, the counter divides the SCLK
frequency by 16, causing the output register to latch
every 16 bits of incoming serial data. The synchroniza-
tion inputs (SYNC+, SYNC-) realign and reframe data.
When the SYNC signal is pulsed high for at least four
SCLK cycles, the parallel output data is delayed by one
SCLK cycle. This realignment is guaranteed to occur
within two complete PCLK cycles of the SYNC signal’s
positive transition. As a result, the first incoming bit of
data during that PCLK cycle is dropped, shifting the
alignment between PCLK and data by one bit. See
Figure 3 for the timing diagram and Figure 4 for the tim-
ing parameters diagram.
Low-Voltage Differential-Signal (LVDS)
Inputs and Outputs
The MAX3885 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifica-
tion. This technology uses 500mVp-p to 800mVp-p dif-
ferential low-voltage swings to achieve fast transition
times, minimize power dissipation, and improve noise
immunity. The parallel clock and data LVDS outputs
(PCLK+, PCLK-, PD_+, PD_-) require 100Ω differential
D15 D14 D13
SCLK
SD
SYNC
PCLK
(LSB) PD0
D0
D16
PD1
D1
D17
•
•
•
(MSB) PD15
D15
D31
TRANSMITTED FIRST
D32
D48
D65
D33
D49
D66
ONE BIT HAS SLIPPED
IN THIS TIME SLICE
D47
D64
D80
Figure 3. Timing Diagram
_______________________________________________________________________________________ 5
Share Link: 